Datasheet

Flash EEPROM 256K
Register Descriptions
MC9S12DP256 — Revision 1.1
Flash EEPROM 256K
Register Descriptions
NOTE: All bits of all registers in this module are completely synchronous to
internal clocks during a register read.
FCLKDIV Ñ Flash
Clock Divider
Register
Read: Anytime
Write: Once in normal mode, anytime in special mode
This register is unbanked. It is used to divide the external oscillator
frequency down to a frequency required by the program/erase state
machines.
FDIVLD — Flash Clock Divider Loaded
This bit is set when the FCLKDIV register is written to. If this bit is “0”
the register has not been written since the last reset. Trying to
program or erase the flash without having written to this register
previously will result in an access error and the command will not be
executed.
1 = Register has been written to since the last reset.
0 = Register has not been written to.
PRDIV8 — Enable Prescaler by 8
1 = Enables a prescaler by 8 before feeding into the FCLKDIV
divider.
0 = OSCCLK is directly fed into the FCLKDIV divider
Address Offset: $0000
Bit 7 654321Bit 0
Read: FDIVLD
PRDIV8 FDIV5 FDIV4 FDIV3 FDIV2 FDIV1 FDIV0
Write:
Reset: 00000000
= Reserved or unimplemented
Freescale Semiconductor, I
Freescale Semiconductor, Inc.
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