Datasheet

Flash EEPROM 256K
MC9S12DP256 — Revision 1.1
Flash EEPROM 256K
Functional Description
NOTE: All internal program and erase timings are handled by a state machine.
The timebase is derived from the oscillator clock OSCCLK via a
programmable down counter. The command register as well as the
associated address and data registers operate as a buffer and a register
(2-stage FIFO), so that a new command along with the necessary data
and address can be stored to the buffers while the previous command is
still in progress. Buffers empty condition as well as command completion
are signalled by flags in the status register. Interrupts will be generated
if enabled. The main reason for this approach is that the maximum
high-voltage active time for a flash row is limited to t
HV.
Starting and
stopping the high voltage after every word however would increase the
programming time by a factor of two. The internal programming state
machine will therefore keep the high voltage circuitry alive if a new
program command operating on the same flash row (only address bits
A[5:1] are allowed to change) is available, when the current program
command is completed. The next programming cycle can then start
without a delay. However if the command has changed, the address is
not within the same row or the command buffer is empty, the high
voltage will be turned off and restarted with the new command if
required.
Program and
Erase Procedures
Prior to issuing any program or erase commands it is necessary to
program the FCLKDIV register to divide the oscillator clock to within the
150KHz to 200KHz range. Program and erase commands will not
function if this register has not been initialized. See FCLKDIV register
description for further details.
A Command State Machine, shared between all four flash blocks, is
used to supervise the command sequence.
To prepare for a program or erase command sequence it is necessary
to set the PPAGE and FCNFG registers as follows:
1. Write to bits BKSEL[1:0] in the FCNFG register to select the bank
of registers associated with the 64K flash block to be programmed
or erased (i.e. Flash 0, 1, 2 or 3) See Figure 17 for further details.
Freescale Semiconductor, I
Freescale Semiconductor, Inc.
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