Datasheet
Table Of Contents
- List of Sections
- Table of Contents
- General Description
- Central Processing Unit (CPU)
- Pinout and Signal Description
- System Configuration
- Registers
- Operating Modes
- Resource Mapping
- Bus Control and Input/Output
- Resets and Interrupts
- Voltage Regulator (VREG)
- Flash EEPROM 256K
- EEPROM 4K
- Port Integration Module
- Clocks and Reset Generator (CRG)
- Pulse Width Modulator (PWM)
- Enhanced Capture Timer (ECT)
- Serial Communications Interface (SCI)
- Serial Peripheral Interface (SPI)
- Inter-IC Bus (IIC)
- MSCAN
- Analog to Digital Converter
- Byte Data Link Controller Module
- Contents
- Overview
- Features
- Block Diagram
- Register Map
- Functional Description
- Register Descriptions
- External Pin Descriptions
- Reset Initialization/Basic Operation
- Transmitting A Message
- Receiving A Message
- Transmitting An In-Frame Response (IFR)
- Receiving An In-Frame Response (IFR)
- Special BDLC Operations
- Modes of Operation
- Interrupt Operation
- Low Power Options
- Background Debug Module (BDM)
- Breakpoint (BKP) Module
- Revision History
- Glossary
- Literature Updates

Flash EEPROM 256K
MC9S12DP256 — Revision 1.1
Flash EEPROM 256K
Flash Protection
Option Fields
Flash block 0 also holds a field of 16-bytes containing Security,
Protection as well as “backdoor” comparison bytes. The layout of this
field is as follows:
Register Memory
Map
In order to accommodate several flash blocks with a minimum of register
address space, a set of registers ($_104–$_10B) are duplicated in four
banks. The active bank is selected by the bits BKSEL[1:0] in the
unbanked Flash Configuration Register (FCNFG).
Table 28 Flash 0 Protection/Security Field
Address Size Description
$FF00–$FF07 8 Backdoor comparison key
$FF08–$FF09 2 Reserved
$FF0A 1 Protection byte for Flash block 3
$FF0B 1 Protection byte for Flash block 2
$FF0C 1 Protection byte for Flash block 1
$FF0D 1 Protection byte for Flash block 0
$FF0E 1 Reserved
$FF0F 1 Security Byte
Register name Bit 7 654321Bit 0
Addr.
Offset
FCLKDIV
Read: FDIVLD
PRDIV8 FDIV5 FDIV4 FDIV3 FDIV2 FDIV1 FDIV0 $0000
Write:
FSEC
Read: KEYEN NV6 NV5 NV4 NV3 NV2 SEC01 SEC00
$0001
Write:
Reserved for
Factory Test
Read: 00000000
$0002
Write:
Reset:
FCNFG
Read:
CBEIE CCIE KEYACC
000
BKSEL1 BKSEL0 $0003
Write:
Unbanked Registers
Banked Registers
= Unimplemented or reserved
Figure 19 Flash Control Register Map
Freescale Semiconductor, I
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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