Datasheet

Voltage Regulator (VREG)
Functional Description
MC9S12DP256 — Revision 1.1
Voltage Regulator (VREG)
Functional Description
The voltage regulator module generates the supply voltage needed for
the core logic as well as for the oscillator/pll section. The reference for
the regulation loops are derived from a voltage divider connected
between VDDA and VSSA. Both regulation loops, VDD and VDDPLL,
consist of an operational amplifier driving an nmos power transistor in
unit gain configuration. If there is no significant demand of output current
(the CPU is in stop or pseudo stop mode) the voltage regulator is brought
into standby mode, to decrease power consumption of the voltage
regulator itself.
The voltage regulator can be enabled/disabled by the logic level on the
VREGEN pin.
The level of VDD is internally monitored to generate a power on reset
signal. If VDD is below V
PORA
reset will be asserted and a power on
reset sequence will be triggered as soon as VDD rises above V
PORR
.
Change of VDDA or VSSA levels will directly influence the voltage levels
at VDD and VDDPLL. Because of this reason, it is sufficient to monitor
the level of VDDA externally to generate a system reset if the supply
voltage is out of specification limits.
Please note VDDA, VDDR and VSSX are internally connected by anti
parallel diodes.
External Pin Connection
The PCB must be carefully laid out to ensure proper operation of the
voltage regulator as well as of the MCU itself. The following rules must
be observed:
• Every supply pair must be decoupled by a ceramic capacitor
connected as near as possible to the corresponding pins (C1 –
C6).
• Central point of the ground star should be the VSSR pin.
Freescale Semiconductor, I
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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