Datasheet
Table Of Contents
- List of Sections
- Table of Contents
- General Description
- Central Processing Unit (CPU)
- Pinout and Signal Description
- System Configuration
- Registers
- Operating Modes
- Resource Mapping
- Bus Control and Input/Output
- Resets and Interrupts
- Voltage Regulator (VREG)
- Flash EEPROM 256K
- EEPROM 4K
- Port Integration Module
- Clocks and Reset Generator (CRG)
- Pulse Width Modulator (PWM)
- Enhanced Capture Timer (ECT)
- Serial Communications Interface (SCI)
- Serial Peripheral Interface (SPI)
- Inter-IC Bus (IIC)
- MSCAN
- Analog to Digital Converter
- Byte Data Link Controller Module
- Contents
- Overview
- Features
- Block Diagram
- Register Map
- Functional Description
- Register Descriptions
- External Pin Descriptions
- Reset Initialization/Basic Operation
- Transmitting A Message
- Receiving A Message
- Transmitting An In-Frame Response (IFR)
- Receiving An In-Frame Response (IFR)
- Special BDLC Operations
- Modes of Operation
- Interrupt Operation
- Low Power Options
- Background Debug Module (BDM)
- Breakpoint (BKP) Module
- Revision History
- Glossary
- Literature Updates
General Description
MC9S12DP256 — Revision 1.1
General Description
MC9S12DP256 112-Pin Block Diagram
256K Byte Flash EEPROM
12K Byte RAM
Enhanced Capture
RESET
EXTAL
XTAL
V
DD1,2
V
SS1,2
SCI0
4K Byte EEPROM
BKGD
R/W
MODB
XIRQ
NOACC/XCLKS
System
Integration
Module
V
DDR
CPU12
Periodic Interrupt
COP Watchdog
Clock Monitor
Single-wire
Breakpoints
PLL
V
SSPLL
XFC
V
DDPLL
Multiplexed Address/Data Bus
VDDA
VSSA
VRH
VRL
ATD0
Multiplexed
Wide Bus
Multiplexed
V
DDX
V
SSX
Internal Logic 2.5V
Narrow Bus
PPAGE
V
DDPLL
V
SSPLL
PLL 2.5V
IRQ
LSTRB
ECLK
MODA
PA4
PA3
PA2
PA1
PA0
PA7
PA6
PA5
TEST
ADDR12
ADDR11
ADDR10
ADDR9
ADDR8
ADDR15
ADDR14
ADDR13
DATA12
DATA11
DATA10
DATA 9
DATA 8
DATA15
DATA14
DATA13
PB4
PB3
PB2
PB1
PB0
PB7
PB6
PB5
ADDR4
ADDR3
ADDR2
ADDR1
ADDR0
ADDR7
ADDR6
ADDR5
DATA 4
DATA 3
DATA 2
DATA 1
DATA 0
DATA 7
DATA 6
DATA 5
DATA 4
DATA 3
DATA 2
DATA 1
DATA 0
DATA 7
DATA 6
DATA 5
PE3
PE4
PE5
PE6
PE7
PE0
PE1
PE2
AN2
AN6
AN0
AN7
AN1
AN3
AN4
AN5
PAD03
PAD04
PAD05
PAD06
PAD07
PAD00
PAD01
PAD02
IOC2
IOC6
IOC0
IOC7
IOC1
IOC3
IOC4
IOC5
PT3
PT4
PT5
PT6
PT7
PT0
PT1
PT2
V
RH
V
RL
VDDA
VSSA
VRH
VRL
ATD1
AN2
AN6
AN0
AN7
AN1
AN3
AN4
AN5
PAD11
PAD12
PAD13
PAD14
PAD15
PAD08
PAD09
PAD10
V
DDA
V
SSA
RXD
TXD
MISO
MOSI
PS3
PS4
PS5
PS0
PS1
PS2
SCI1
RXD
TXD
PWM
PWM2
PWM6
PWM0
PWM7
PWM1
PWM3
PWM4
PWM5
PP3
PP4
PP5
PP6
PP7
PP0
PP1
PP2
PIX2
PIX0
PIX1
PIX3
ROMONE/ECS
PK3
PK7
PK0
PK1
XADDR17
ECS
XADDR14
XADDR15
XADDR16
SCK
SS
PS6
PS7
SPI0
IIC
SDA
SCL
PJ6
PJ7
CAN0
RxCAN
TxCAN
PM1
PM0
CAN1
RxCAN
TxCAN
PM2
PM3
CAN2
RxCAN
TxCAN
PM4
PM5
CAN3
RxCAN
TxCAN
PM6
PM7
Pin
KWH2
KWH6
KWH0
KWH7
KWH1
KWH3
KWH4
KWH5
PH3
PH4
PH5
PH6
PH7
PH0
PH1
PH2
KWJ0
KWJ1
PJ0
PJ1
I/O Driver 5V
V
DDA
V
SSA
A/D Converter 5V &
DDRA DDRB
PTA PTB
DDRE
PTE
AD1
AD0
PTK
DDRK
PTT
DDRT
PTP
DDRP
PTS
DDRS
PTM
DDRM
PTH
DDRH
PTJ
DDRJ
PK2
BDLC (J1850)
RxB
TxB
Interrupt
Logic
Clock and
Reset
Generation
Module
Voltage Regulator
V
SSR
Background
V
DD1,2
V
SS1,2
VREGEN
V
DDR
V
SSR
Voltage Regulator 5V & I/O
CAN4
RxCAN
TxCAN
MISO
MOSI
SS
SCK
SPI2
MISO
MOSI
SCK
SS
SPI1
PIX4
PIX5
PK4
PK5
XADDR18
XADDR19
Voltage Regulator Reference
KWP2
KWP6
KWP0
KWP7
KWP1
KWP3
KWP4
KWP5
KWJ6
KWJ7
Timer
Debug Module
Note: This block diagram is for the 112-pin version. Pins in
bold are not availble in the 80-pin version.
Freescale Semiconductor, I
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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