Datasheet

Resets and Interrupts
Effects of Reset
MC9S12DP256 — Revision 1.1
Resets and Interrupts
Effects of Reset
When a reset occurs, MCU registers and control bits are changed to
known start-up states, as follows.
Operating Mode
and Memory Map
Operating mode and default memory mapping are determined by the
states of the BKGD, MODA, and MODB pins during reset. The MODA,
MODB, and MODC bits in the MODE register reflect the status of the
mode-select inputs at the rising edge of reset. Operating mode and
default maps can subsequently be changed according to strictly defined
rules.
Clock and
Watchdog Control
Logic
The COP watchdog system is enabled, with the CR[2:0] bits set for the
longest duration time-out. The clock monitor is disabled. The RTIF flag
is cleared and automatic hardware interrupts are masked. The rate
control bits are cleared, and must be initialized before the RTI system is
used.
Interrupts PSEL is initialized in the HPRIO register with the value $F2, causing the
external IRQ
pin to have the highest I-bit interrupt priority. The IRQ pin
is configured for level-sensitive operation (for wired-OR systems).
However, the interrupt mask bits in the CPU12 CCR are set to mask X-
and I-related interrupt requests.
Parallel I/O If the MCU comes out of reset in a single-chip mode, all ports are
configured as general-purpose high-impedance inputs.
If the MCU comes out of reset in an expanded mode, port A and port B
are used for the address/data bus, and port E pins are normally used to
control the external bus (operation of port E pins can be affected by the
PEAR register). Out of reset, port K, port E, port H, port J, port M, port T,
port S, port P, port ATD0 and port ATD1 are all configured as
general-purpose inputs.
Freescale Semiconductor, I
Freescale Semiconductor, Inc.
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