Datasheet

Resets and Interrupts
MC9S12DP256 — Revision 1.1
Resets and Interrupts
When COP is enabled, the program must write $55 and $AA (in this
order) to the ARMCOP register during the selected time-out period.
Once this is done, the internal COP counter resets to the start of a new
time-out period. If the program fails to do this the part will reset. Also, if
any value other than $55 or $AA is written, the part is immediately reset.
Windowed COP operation is enabled by setting WCOP in the COPCTL
register. In this mode, writes to the ARMCOP register must occur in the
last 25% of the selected time-out period. A premature write will
immediately reset the part.
To reset the internal COP counter to the start of a COP time-out period,
set both the RTI rate select bits RTICTL[6:0] and the COP rate select bits
COPCTL[2:0] to zero.
Clock Monitor
Reset
If clock frequency falls below a predetermined limit when the clock
monitor is enabled, a reset occurs.
The clock monitor circuit is based on an internal resistor-capacitor (RC)
time delay. If no external clock edges are detected within this RC time
delay, the clock monitor generates a system reset. The clock monitor
function is enabled/disabled by the CME control bit in the PLLCTL
register. This time-out is based on an RC delay so that the clock monitor
can operate without any MCU clocks.
The input to the clock monitor is the reference clock (REFCLK.)
Freescale Semiconductor, I
Freescale Semiconductor, Inc.
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