Datasheet

Resets and Interrupts
Resets
MC9S12DP256 — Revision 1.1
Resets and Interrupts
External Reset External circuitry connected to the RESET pin should not include a large
capacitance that would interfere with the ability of this signal to rise to a
valid logic one within 32 ECLK cycles after the low drive is released.
Upon detection of any reset, an internal circuit drives the RESET
pin low
and a clocked reset sequence controls when the MCU can begin normal
processing.
NOTE: Entry into reset is asynchronous and does not require a clock. However,
the MCU cannot sequence out of reset without a system clock.
In the case of POR or a clock monitor failure, a 4096 ECLK cycle
oscillator startup delay is imposed before the reset recovery sequence
starts (RESET
is driven low throughout this 4096 cycle delay.) The
internal reset recovery sequence then drives RESET
low for 64 to 65
ECLK cycles and releases the drive to allow RESET
to rise. 32 ECLK
cycles later this circuit samples the RESET
pin to see if it has risen to a
logic one level. If RESET
is low at this point, the reset is assumed to be
coming from an external request and the internally latched states of the
COP timeout and clock monitor failure are cleared so the normal reset
vector ($FFFE:FFFF) is taken when RESET
is finally released. If RESET
is high after this 32 cycle delay, the reset source is tentatively assumed
to be either a COP failure or a clock monitor failure. If the internally
latched state of the clock monitor fail circuit is true, processing begins by
fetching the clock monitor vector ($FFFC:FFFD). If no clock monitor
failure is indicated, and the latched state of the COP timeout is true,
processing begins by fetching the COP vector ($FFFA:FFFB). If neither
clock monitor fail nor COP timeout are pending, processing begins by
fetching the normal reset vector ($FFFE:FFFF).
COP Reset The COP watchdog enables the user to check that a program is running
and sequencing properly. When the COP is being used, software is
responsible for keeping a free running watchdog timer from timing out. If
the watchdog timer times out it is an indication that the software is no
longer being executed in the intended sequence; thus a system reset is
initiated. Three control bits in the COPCTL register allow selection of
seven COP time-out periods.
Freescale Semiconductor, I
Freescale Semiconductor, Inc.
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