Datasheet
Table Of Contents
- List of Sections
- Table of Contents
- General Description
- Central Processing Unit (CPU)
- Pinout and Signal Description
- System Configuration
- Registers
- Operating Modes
- Resource Mapping
- Bus Control and Input/Output
- Resets and Interrupts
- Voltage Regulator (VREG)
- Flash EEPROM 256K
- EEPROM 4K
- Port Integration Module
- Clocks and Reset Generator (CRG)
- Pulse Width Modulator (PWM)
- Enhanced Capture Timer (ECT)
- Serial Communications Interface (SCI)
- Serial Peripheral Interface (SPI)
- Inter-IC Bus (IIC)
- MSCAN
- Analog to Digital Converter
- Byte Data Link Controller Module
- Contents
- Overview
- Features
- Block Diagram
- Register Map
- Functional Description
- Register Descriptions
- External Pin Descriptions
- Reset Initialization/Basic Operation
- Transmitting A Message
- Receiving A Message
- Transmitting An In-Frame Response (IFR)
- Receiving An In-Frame Response (IFR)
- Special BDLC Operations
- Modes of Operation
- Interrupt Operation
- Low Power Options
- Background Debug Module (BDM)
- Breakpoint (BKP) Module
- Revision History
- Glossary
- Literature Updates

Resets and Interrupts
MC9S12DP256 — Revision 1.1
Resets and Interrupts
Read: When ADR3–ADR0 have the value of $F, only bits 2–0 in the
ITEST register will be accessible. That is, vectors higher than $FFF4
cannot be tested using the test registers and bits 7–3 will always read
0. If ADR3–ADR0 point to an unimplemented test register, writes will
have no effect and reads will always return 0.
Write: Only in special modes and with WRTINT = 1 and CCR I mask
= 1.
ITEST — Interrupt Test Register
Address Offset: $0016
Bit 7 654321Bit 0
INTE INTC INTA INT8 INT6 INT4 INT2 INT0
Reset:
00000000
Freescale Semiconductor, I
Freescale Semiconductor, Inc.
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