Datasheet

Resets and Interrupts
MC9S12DP256 — Revision 1.1
Resets and Interrupts
Determines which I maskable interrupt will be promoted to highest
priority (of the I maskable interrupts). To promote an interrupt the user
writes the least significant byte of the associated interrupt vector
address to this register. If an unimplemented vector address or a non
I-masked vector address (value higher than $F2) is written, then FFF2
will be the default highest priority interrupt.
READ: Anytime
WRITE: Only if I mask in CCR = 1
Interrupt test
registers
These registers are used in special modes for testing the interrupt logic
and priority without needing to know which modules and what functions
are used to generate the interrupts. Each bit is used to force a specific
interrupt vector by writing it to 1. Bits are named with INTE through INT0
to indicate vectors $FFxE through $FFx0. These bits can be written only
in special modes and only with WRTINT (ITCR bit 4) = 1. In addition,
I-interrupts must be masked using the I bit in the CCR. In this state, the
interrupt input lines to the interrupt module will be disconnected and
interrupts will be caused only through these registers. These bits can
also be read in special modes to view that an interrupt caused by a
module has reached the INT module.
There is a test register for every 8 interrupts implemented in a particular
MCU. All of the test registers share the same address, and are
individually selected using the value stored in the ADR3 – ADR0 bits of
the Interrupt Control Register (ITCR).
NOTE: When ADR3–ADR0 have the value of $F, only bits 2–0 in the ITEST
register will be accessible. That is, vectors higher than $FFF4 cannot be
tested using the test registers and bits 7–3 will always read 0. If
ADR3–ADR0 point to an unimplemented test register, writes will have no
effect and reads will always return 0.
HPRIO — Highest Priority I Interrupt
Address Offset: $001F
Bit 7 654321Bit 0
PSEL7 PSEL6 PSEL5 PSEL4 PSEL3 PSEL2 PSEL1 0
Reset:
11110010
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Freescale Semiconductor, Inc.
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