Datasheet
Table Of Contents
- List of Sections
- Table of Contents
- General Description
- Central Processing Unit (CPU)
- Pinout and Signal Description
- System Configuration
- Registers
- Operating Modes
- Resource Mapping
- Bus Control and Input/Output
- Resets and Interrupts
- Voltage Regulator (VREG)
- Flash EEPROM 256K
- EEPROM 4K
- Port Integration Module
- Clocks and Reset Generator (CRG)
- Pulse Width Modulator (PWM)
- Enhanced Capture Timer (ECT)
- Serial Communications Interface (SCI)
- Serial Peripheral Interface (SPI)
- Inter-IC Bus (IIC)
- MSCAN
- Analog to Digital Converter
- Byte Data Link Controller Module
- Contents
- Overview
- Features
- Block Diagram
- Register Map
- Functional Description
- Register Descriptions
- External Pin Descriptions
- Reset Initialization/Basic Operation
- Transmitting A Message
- Receiving A Message
- Transmitting An In-Frame Response (IFR)
- Receiving An In-Frame Response (IFR)
- Special BDLC Operations
- Modes of Operation
- Interrupt Operation
- Low Power Options
- Background Debug Module (BDM)
- Breakpoint (BKP) Module
- Revision History
- Glossary
- Literature Updates

Resets and Interrupts
Register Descriptions
MC9S12DP256 — Revision 1.1
Resets and Interrupts
Register Descriptions
Interrupt Control
and Priority
Register
IRQE — IRQ Select Edge Sensitive Only
1 = IRQ configured to respond only to falling edges. Falling edges
on the IRQ pin will be detected anytime IRQE = 1 and will be
cleared only upon a reset or the servicing of the IRQ interrupt.
0 = IRQ configured for low-level recognition.
Special: read or write anytime
Normal: read anytime, write once
Emulation: read anytime, write never
IRQEN — External IRQ Enable
1 = External IRQ
pin is connected to interrupt logic.
0 = External IRQ
pin is disconnected from interrupt logic.
Normal, emulation, and special modes: read or write anytime
INTCR — Interrupt Control Register
Address Offset: $001E
Bit 7 654321Bit 0
IRQE IRQEN 000000
Reset:
01000000
Freescale Semiconductor, I
Freescale Semiconductor, Inc.
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