Datasheet
Table Of Contents
- List of Sections
- Table of Contents
- General Description
- Central Processing Unit (CPU)
- Pinout and Signal Description
- System Configuration
- Registers
- Operating Modes
- Resource Mapping
- Bus Control and Input/Output
- Resets and Interrupts
- Voltage Regulator (VREG)
- Flash EEPROM 256K
- EEPROM 4K
- Port Integration Module
- Clocks and Reset Generator (CRG)
- Pulse Width Modulator (PWM)
- Enhanced Capture Timer (ECT)
- Serial Communications Interface (SCI)
- Serial Peripheral Interface (SPI)
- Inter-IC Bus (IIC)
- MSCAN
- Analog to Digital Converter
- Byte Data Link Controller Module
- Contents
- Overview
- Features
- Block Diagram
- Register Map
- Functional Description
- Register Descriptions
- External Pin Descriptions
- Reset Initialization/Basic Operation
- Transmitting A Message
- Receiving A Message
- Transmitting An In-Frame Response (IFR)
- Receiving An In-Frame Response (IFR)
- Special BDLC Operations
- Modes of Operation
- Interrupt Operation
- Low Power Options
- Background Debug Module (BDM)
- Breakpoint (BKP) Module
- Revision History
- Glossary
- Literature Updates

Resets and Interrupts
Latching of Interrupts
MC9S12DP256 — Revision 1.1
Resets and Interrupts
$FFE4, $FFE5 Timer channel 5 I-Bit TMSK1 (C5I) $E4
$FFE2, $FFE3 Timer channel 6 I-Bit TMSK1 (C6I) $E2
$FFE0, $FFE1 Timer channel 7 I-Bit TMSK1 (C7I) $E0
$FFDE, $FFDF Timer overflow I-Bit TMSK2 (TOI) $DE
$FFDC, $FFDD Pulse accumulator A overflow I-Bit PACTL (PAOVI) $DC
$FFDA, $FFDB Pulse accumulator input edge I-Bit PACTL (PAI) $DA
$FFD8, $FFD9 SPI0 I-Bit SP0CR1 (SPIE, SPTIE) $D8
$FFD6, $FFD7 SCI 0 I-Bit
SC0CR2
(TIE, TCIE, RIE, ILIE)
$D6
$FFD4, $FFD5 SCI 1 I-Bit
SC1CR2
(TIE, TCIE, RIE, ILIE)
$D4
$FFD2, $FFD3 ATD0 I-Bit ATD0CTL2 (ASCIE) $D2
$FFD0, $FFD1 ATD1 I-Bit ATD1CTL2 (ASCIE) $D0
$FFCE, $FFCF Port J I-Bit PTJIF (PTJIE) $CE
$FFCC, $FFCD Port H I-Bit PTHIF(PTHIE) $CC
$FFCA, $FFCB Modulus Down Counter underflow I-Bit MCCTL(MCZI) $CA
$FFC8, $FFC9 Pulse Accumulator B Overflow I-Bit PBCTL(PBOVI) $C8
$FFC6, $FFC7 CRG lock I-Bit PLLCR(LOCKIE) $C6
$FFC4, $FFC5 SCME I-Bit PLLCR (SCMIE) $C4
$FFC2, $FFC3 DLC I-Bit DLCBCR1(IE) $C2
$FFC0, $FFC1 IIC Bus I-Bit IBCR (IBIE) $C0
$FFBE, $FFBF SPI1 I-Bit SP1CR1 (SPIE. SPTIE) $BE
$FFBC, $FFBD SPI2 I-Bit SP2CR1 (SPIE, SPTIE) $BC
$FFBA, $FFBB EEPROM I-Bit EECTL(CCIE, CBEIE) $BA
$FFB8, $FFB9 FLASH I-Bit FCTL(CCIE, CBEIE) $B8
$FFB6, $FFB7 MSCAN 0 wake-up I-Bit C0RIER (WUPIE) $B6
$FFB4, $FFB5 MSCAN 0 errors I-Bit
C0RIER (RWRNIE,
TWRNIE, RERRIE,
TERRE, BOFFIE,
OVRIE)
$B4
$FFB2, $FFB3 MSCAN 0 receive I-Bit C0RIER (RXFIE) $B2
$FFB0, $FFB1 MSCAN 0 transmit I-Bit C0TIER(TXEIE[2:0] $B0
$FFAE, $FFAF MSCAN 1 wake-up I-Bit C1RIER (WUPIE) $AE
$FFAC, $FFAD MSCAN 1 errors I-Bit
C1RIER (RWRNIE,
TWRNIE, RERRIE,
TERRE, BOFFIE,
OVRIE)
$AC
$FFAA, $FFAB MSCAN 1 receive I-Bit C1RIER (RXFIE) $AA
$FFA8, $FFA9 MSCAN 1 transmit I-Bit C1TIER(TXEIE[2:0] $A8
$FFA6, $FFA7 MSCAN 2 wake-up I-Bit C2RIER (WUPIE) $A6
Table 24 Interrupt Vector Table
Freescale Semiconductor, I
Freescale Semiconductor, Inc.
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