Datasheet

Resets and Interrupts
Maskable interrupts
MC9S12DP256 — Revision 1.1
Resets and Interrupts
Maskable interrupts
Maskable interrupt sources include on-chip peripheral systems and
external interrupt service requests. Interrupts from these sources are
recognized when the global interrupt mask bit (I) in the CCR is cleared. The
default state of the I bit out of reset is one, but it can be written at any time.
Interrupt sources are prioritized by default but any one maskable interrupt
source may be assigned the highest priority by means of the HPRIO
register. The relative priorities of the other sources remain the same.
An interrupt that is assigned highest priority is still subject to global
masking by the I bit in the CCR, or by any associated local bits. Interrupt
vectors are not affected by priority assignment. HPRIO can only be
written while the I bit is set (interrupts inhibited). Table 24 lists interrupt
sources and vectors in default order of priority. Before masking an
interrupt by clearing the corresponding local enable bit, it is required to
set the I-bit to avoid an SWI.
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