Datasheet

MC9S12DP256 — Revision 1.1
Resets and Interrupts
Resets and Interrupts
Resets and Interrupts
Contents
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
Register Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
Exception Priority . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
Maskable interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143
Latching of Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144
Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
Resets. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
Effects of Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155
Register Stacking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157
Introduction
STAR12 exceptions include resets and interrupts. Each exception has
an associated 16-bit vector, which points to the memory location where
the routine that handles the exception is located. Vectors are stored in
the upper 128 bytes of the standard 64K byte address map.
The six highest vector addresses are used for resets and non-maskable
interrupt sources. The remainder of the vectors are used for maskable
interrupts, and all must be initialized to point to the address of the
appropriate service routine.
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