Datasheet

Bus Control and Input/Output
MC9S12DP256 — Revision 1.1
Bus Control and Input/Output
Port E serves as general purpose I/O lines or as system and bus
control signals. The PEAR register is used to choose between the
general-purpose I/O functions and the alternate bus control functions.
When an alternate control function is selected, the associated DDRE
bits are overridden.
The reset condition of this register depends on the mode of operation
because bus control signals are needed immediately after reset in
some modes.
In normal single chip mode, no external bus control signals are
needed so all of Port E is configured for general purpose I/O.
In normal expanded modes, only the E clock is configured for its
alternate bus control function and the other bits of Port E are
configured for general purpose I/O. As the reset vector is located in
external memory, the E clock is required for this access. R/W
is only
needed by the system when there are external writable resources. If
the normal expanded system needs any other bus control signals,
PEAR would need to be written before any access that needed the
additional signals.
In special test and emulation modes, IPIPE1, IPIPE0, E, LSTRB
and
R/W
are configured out of reset as bus control signals.
PEAR — Port E Assignment Register
Address Offset: $000A
Bit 7 654321Bit 0
NOACCE 0 PIPOE NECLK LSTRE RDWE 0 0
Reset:
00000000
Special sin-
gle chip
Reset:
00101100
Special
Test
Reset: 00000000Peripheral
Reset:
10101100
Emulation
Exp Nar
Reset:
10101100
Emulation
Exp Wide
Reset:
00010000
Normal
Single Chip
Reset:
00000000
Normal Exp
Nar
Reset:
00000000
Normal Exp
Wide
Freescale Semiconductor, I
Freescale Semiconductor, Inc.
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