Datasheet

Bus Control and Input/Output
Registers
MC9S12DP256 — Revision 1.1
Bus Control and Input/Output
Data Direction Register E is associated with Port E. For bits in Port E
that are configured as general purpose I/O lines, DDRE determines
the primary direction of each of these pins. A “1” causes the
associated bit to be an output and a “0” causes the associated bit to
be an input. Port E bit 1 (associated with IRQ
) and bit 0 (associated
with XIRQ
) cannot be configured as outputs. Port E, bit 1, and bit 0
can be read regardless of whether the alternate interrupt function is
enabled. The value in a DDR bit also affects the source of data for
reads of the corresponding PORTE register. If the DDR bit is zero
(input) the buffered pin input is read. If the DDR bit is one (output) the
output of the port data latch is read.
This register is not in the on-chip map in peripheral mode. It is also not
in the map in expanded modes while the EME control bit is set.
Read and write: anytime (provided this register is in the map).
DDRE7–2 — Data Direction Port E
0 = Configure the corresponding I/O pin as an input
1 = Configure the corresponding I/O pin as an output
DDRE — Port E Data Direction Register
Address Offset: $0009
Bit 7 654321Bit 0
Bit 7 6543Bit 2 00
Reset: 00000000
Freescale Semiconductor, I
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
nc...