Datasheet

Bus Control and Input/Output
MC9S12DP256 — Revision 1.1
Bus Control and Input/Output
Port E is associated with external bus control signals and interrupt
inputs. These include mode select (XCLKS
/NOACC, MODB/IPIPE1,
MODA/IPIPE0), E clock, size (LSTRB
/TAGLO), read / write (R/W),
IRQ
, and XIRQ. When the associated pin is not used for one of these
specific functions, the pin can be used as general purpose I/O. The
Port E Assignment Register (PEAR) selects the function of each pin
and DDRE determines whether each pin is an input or output when it
is configured to be general purpose I/O. DDRE also determines the
source of data for a read of PORTE.
Some of these pins have software selectable pullups (PE7, ECLK,
LSTRB
, R/W, IRQ and XIRQ). A single control bit enables the pullups
for all of these pins when they are configured as inputs.
This register is not in the on-chip map in peripheral mode or in
expanded modes when the EME bit is set.
Read and write: anytime (provided this register is in the map).
CAUTION: It is unwise to write PORTE and DRRE as a word access. If you are
changing PORT E pins from being inputs to outputs, the data may have
extra transitions during the write. It is best to initialize PORTE before
enabling as outputs.
CAUTION: To ensure that you read the value present on the PORTE pins, always
wait at least two cycles after writing to the DDRE register before reading
from the PORTE register.
PORTE — Port E Register
Address Offset: $0008
Bit 7 654321Bit 0
Bit 7 654321Bit 0
Reset: Unaffected by reset
Alt. Pin
Function
XCLKS
or
NOACC
MODB or
IPIPE1 or
SCGTO
MODA or
IPIPE0 or
RCRTO
ECLK
LSTRB or
TAGLO
R/W IRQ XIRQ
Freescale Semiconductor, I
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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