Datasheet

Bus Control and Input/Output
Registers
MC9S12DP256 — Revision 1.1
Bus Control and Input/Output
This register controls the data direction for Port B. When Port B is
operating as a general purpose I/O port, DDRB determines the
primary direction for each Port B pin. A “1” causes the associated port
pin to be an output and a “0” causes the associated pin to be a
high-impedance input. The value in a DDR bit also affects the source
of data for reads of the corresponding PORTB register. If the DDR bit
is zero (input) the buffered pin input is read. If the DDR bit is one
(output) the output of the port data latch is read.
This register is not in the on-chip map in expanded and peripheral
modes. It is reset to $00 so the DDR does not override the three-state
control signals.
Read and write: anytime (provided this register is in the map).
DDRB7–0 — Data Direction Port B
0 = Configure the corresponding I/O pin as an input
1 = Configure the corresponding I/O pin as an output
DDRB — Port B Data Direction Register
Address Offset: $0003
Bit 7 654321Bit 0
Bit 7 654321Bit 0
Reset: 00000000
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