Datasheet

Bus Control and Input/Output
Registers
MC9S12DP256 — Revision 1.1
Bus Control and Input/Output
This register controls the data direction for Port A. When Port A is
operating as a general purpose I/O port, DDRA determines the
primary direction for each Port A pin. A “1” causes the associated port
pin to be an output and a “0” causes the associated pin to be a
high-impedance input. The value in a DDR bit also affects the source
of data for reads of the corresponding PORTA register. If the DDR bit
is zero (input) the buffered pin input is read. If the DDR bit is one
(output) the output of the port data latch is read.
This register is not in the on-chip map in expanded and peripheral
modes. It is reset to $00 so the DDR does not override the three-state
control signals.
Read and write: anytime (provided this register is in the map).
DDRA7–0 — Data Direction Port A
0 = Configure the corresponding I/O pin as an input
1 = Configure the corresponding I/O as an output
Port B bits 7 through 0 are associated with address lines A7 through
A0 respectively and data lines D7 through D0 respectively. When this
port is not used for external addresses, such as in single-chip mode,
DDRA — Port A Data Direction Register
Address Offset: $0002
Bit 7 654321Bit 0
BIT 7 654321BIT 0
Reset: 00000000
PORTB — Port B Register
Address Offset: $0001
Bit 7 654321Bit 0
Single Chip Bit 7 654321Bit 0
Reset: Unaffected by reset
Expanded
& Periph:
ADDR7/
DATA7
ADDR6/
DATA6
ADDR5/
DATA5
ADDR4/
DATA4
ADDR3/
DATA3
ADDR2/
DATA2
ADDR1/
DATA1
ADDR0/
DATA0
Expanded
narrow
ADDR7 ADDR6 ADDR5 ADDR4 ADDR3 ADDR2 ADDR1 ADDR0
Freescale Semiconductor, I
Freescale Semiconductor, Inc.
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