Datasheet

Bus Control and Input/Output
MC9S12DP256 — Revision 1.1
Bus Control and Input/Output
• Start odd – This state indicates the current opcode is located in the
top of the queue, low byte.
The MEBI sub-block modifies the CPU pipe signals on cycles that are
not controlled by the CPU so that an external development system can
interpret the status information in a consistent way. The modification
forces 0:0 indications on the external pipe signals on Port E, bits 6 and
5 during the extra external E clock edges when the CPU clock is
stopped.
Four types of bus accesses cause an interruption to the normal flow of
this information. The first case is called a bus steal which is caused when
another module has to steal a bus cycle (i.e. BDM access). The second
case is called a hold which is caused when another module needs to
stop the cycle (i.e. splitting a 16-bit access into two separate 8-bit
accesses or a stretch cycle to accommodate a slow memory access).
The CPU clocks are stopped during these accesses. The last cases are
combinations of hold followed by bus steal or bus steal followed by hold.
During these accesses, the internal bus clock is free running.
Table 22 Pipe Status Signals IPIPE[1:0], E Clock High
Data Movement Mnemonic Meaning
0:0 – No movement
1:0 ALD Advance queue, load from bus
Table 23 Pipe Status Signals IPIPE[1:0], E Clock Low
Execution Start Mnemonic Meaning
0:0 – No start
0:1 INT Start interrupt sequence
1:0 SEV Start even instruction
1:1 SOD Start odd instruction
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