Datasheet

Bus Control and Input/Output
PIPE Status Signals
MC9S12DP256 — Revision 1.1
Bus Control and Input/Output
PIPE Status Signals
PIPE status signals IPIPE[1:0] provide information about data
movement in the queue and indicate when the CPU begins to execute
instructions. This makes it possible to monitor CPU activity on a
cycle-by-cycle basis for debugging. Information available on the
IPIPE[1:0] pins is time multiplexed.
Data movement (valid during E-clock high) is represented by two states:
• Advance and load from bus – This state means the queue shifts
up one stage with stage 1 being filled with the instruction on the
bus.
• No movement – This state means there is no data shifting in the
queue.
The execution start (valid during E-clock low) is represented by four
states:
• No start – This state indicates a continuation of the current
instruction.
• Start interrupt – This state indicates that an interrupt sequence
has begun.
NOTE: The start interrupt state is indicated when an external signal alters
program flow (i.e. interrupt request, force or tag). SWI and TRAP
instructions in the instruction pipe are indicated as start even or start odd
depending on their alignment. In this case, the SWI and TRAP
instructions are part of the normal program flow. Since they are present
in the queue, they may be tracked in an external pipe rebuild. An external
event that interrupts program flow is indeterministic. Program data is not
present in the queue until after the vector jump.
• Start even – This state indicates the current opcode is located in
the top of the queue, high byte.
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Freescale Semiconductor, Inc.
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