Datasheet

Bus Control and Input/Output
MC9S12DP256 — Revision 1.1
Bus Control and Input/Output
Stretched Bus Cycles
In order to allow fast internal bus cycles to coexist in a system with
slower external memory resources, the STAR12 supports the concept of
stretched bus cycles (module timing reference clocks for timers and
baud rate generators are not affected by this stretching). Control
registers specify the amount of stretch (0, 1, 2, or 3 periods of the internal
bus-rate clock). While stretching, the CPU clocks are halted during the
E clock high period of an unstretched bus cycle. At this point in the CPU
bus cycle, write data would already be driven onto the data bus so the
length of time write data is valid is extended in the case of a stretched
bus cycle. Read data would not be captured by the MCU until the E clock
falling edge. In the case of a stretched bus cycle, read data is not
required until the specified setup time before the falling edge of the
stretched E clock. The external address and R/W signals remain valid
during the period of stretching (throughout the stretched E high time).
Table 21 Access Type vs. Bus Control Pins
LSTRB A0 R/W Type of Access
1 0 1 8-bit read of an even address
0 1 1 8-bit read of an odd address
1 0 0 8-bit write of an even address
0 1 0 8-bit write of an odd address
0 0 1 16-bit read of an even address
111
16-bit read of an odd address
(low/high data swapped)
0 0 0 16-bit write to an even address
110
16-bit write to an odd address
(low/high data swapped)
Freescale Semiconductor, I
Freescale Semiconductor, Inc.
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