Datasheet

MC9S12DP256 — Revision 1.1
Bus Control and Input/Output
Bus Control and Input/Output
Bus Control and Input/Output
Contents
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
Detecting Access Type from External Signals . . . . . . . . . . . . . . . . . 123
Stretched Bus Cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
PIPE Status Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
Introduction
Internally the MC9S12DP256 has full 16-bit data paths, but depending
upon the operating mode and control registers, the external multiplexed
bus may be 8 or 16 bits. There are cases where 8-bit and 16-bit
accesses can appear on adjacent cycles using the LSTRB
signal to
indicate 8- or 16-bit data.
Detecting Access Type from External Signals
The external signals LSTRB, R/W, and A0 indicate the type of bus
access that is taking place. Accesses to the internal RAM module are the
only type of access that produce LSTRB
= A0 = 1, because the internal
RAM is specifically designed to allow misaligned 16-bit accesses in a
single cycle. In these cases the data for the address that was accessed
is on the low half of the data bus and the data for address + 1 is on the
high half of the data bus.
Freescale Semiconductor, I
Freescale Semiconductor, Inc.
For More Information On This Product,
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