Datasheet
Table Of Contents
- List of Sections
- Table of Contents
- General Description
- Central Processing Unit (CPU)
- Pinout and Signal Description
- System Configuration
- Registers
- Operating Modes
- Resource Mapping
- Bus Control and Input/Output
- Resets and Interrupts
- Voltage Regulator (VREG)
- Flash EEPROM 256K
- EEPROM 4K
- Port Integration Module
- Clocks and Reset Generator (CRG)
- Pulse Width Modulator (PWM)
- Enhanced Capture Timer (ECT)
- Serial Communications Interface (SCI)
- Serial Peripheral Interface (SPI)
- Inter-IC Bus (IIC)
- MSCAN
- Analog to Digital Converter
- Byte Data Link Controller Module
- Contents
- Overview
- Features
- Block Diagram
- Register Map
- Functional Description
- Register Descriptions
- External Pin Descriptions
- Reset Initialization/Basic Operation
- Transmitting A Message
- Receiving A Message
- Transmitting An In-Frame Response (IFR)
- Receiving An In-Frame Response (IFR)
- Special BDLC Operations
- Modes of Operation
- Interrupt Operation
- Low Power Options
- Background Debug Module (BDM)
- Breakpoint (BKP) Module
- Revision History
- Glossary
- Literature Updates

Resource Mapping
MC9S12DP256 — Revision 1.1
Resource Mapping
Figure 8 MC9S12DP256 Memory Map after reset
* Assuming that a ‘0’ was driven onto port K bit 7 during reset.
$0400
$0000
$1000
$4000
$8000
$C000
$FF00
VECTORS
$FFFF
EXTERN
EXPANDED*
VECTORS
NORMAL
SINGLE CHIP
VECTORS
SPECIAL
SINGLE CHIP
REGISTERS
(Mappable to any 2k Block
within the first 32K)
$0000
$03FF
$0000
$0FFF
4K Bytes EEPROM
(Mappable to any 4K Block)
12K Bytes RAM
(Mappable to any 16K
$1000
$3FFF
and alignable to top or
bottom)
$4000
$7FFF
16K Fixed Flash
Page $3E = 62
(This is dependant on the
state of the ROMHM bit)
$8000
$BFFF
16K Page Window
16 x 16K Flash EEPROM
pages
$C000
$FFFF
16K Fixed Flash
Page $3F = 63
$FF00
$FFFF
BDM
(if active)
Freescale Semiconductor, I
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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