Datasheet
Table Of Contents
- List of Sections
- Table of Contents
- General Description
- Central Processing Unit (CPU)
- Pinout and Signal Description
- System Configuration
- Registers
- Operating Modes
- Resource Mapping
- Bus Control and Input/Output
- Resets and Interrupts
- Voltage Regulator (VREG)
- Flash EEPROM 256K
- EEPROM 4K
- Port Integration Module
- Clocks and Reset Generator (CRG)
- Pulse Width Modulator (PWM)
- Enhanced Capture Timer (ECT)
- Serial Communications Interface (SCI)
- Serial Peripheral Interface (SPI)
- Inter-IC Bus (IIC)
- MSCAN
- Analog to Digital Converter
- Byte Data Link Controller Module
- Contents
- Overview
- Features
- Block Diagram
- Register Map
- Functional Description
- Register Descriptions
- External Pin Descriptions
- Reset Initialization/Basic Operation
- Transmitting A Message
- Receiving A Message
- Transmitting An In-Frame Response (IFR)
- Receiving An In-Frame Response (IFR)
- Special BDLC Operations
- Modes of Operation
- Interrupt Operation
- Low Power Options
- Background Debug Module (BDM)
- Breakpoint (BKP) Module
- Revision History
- Glossary
- Literature Updates

Resource Mapping
Flash EEPROM mapping through internal Memory Expansion
MC9S12DP256 — Revision 1.1
Resource Mapping
Page Index
register
descriptions
Read and write anytime
Writes do not change pin state when pin configured for page index
emulation output.
This port is associated with the internal memory expansion emulation
pins. When the port is not enabled to emulate the internal memory
expansion, the port pins are used as general-purpose I/O. This register
is not in the map in peripheral mode or in expanded modes while the
EMK bit in the MODE register is set.
When inputs, these pins can be selected to be high impedance or pulled
up based upon the state of the PUPKE bit in the PUCR register (in the
MEBI).
Bit 7— Port K bit 7.
This bit is used as an emulation chip select signal for the emulation of
the internal memory expansion, or as general purpose I/O, depending
upon the state of the EMK bit in the MODE register. See Table 18
Expanded address decode for additional details on when this signal
will be active.
The value on this pin during reset determines the reset state of the
ROMON bit during reset into all expanded modes.
PORTK — Port K Data Register
Address Offset: $0032
Bit 7 6 5 4 3 2 1 Bit 0
Port:
Bit 7 6 0 0 0 2 1 Bit 0
Reset: Unaffected by reset
Alt. pin
function
ECS/
ROMONE
0 XAB19 XAB18 XAB17 XAB16 XAB15 XAB14
Freescale Semiconductor, I
Freescale Semiconductor, Inc.
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Go to: www.freescale.com
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