Datasheet

Resource Mapping
MC9S12DP256 — Revision 1.1
Resource Mapping
Read: Anytime.
Reset: $09 (RAM located from $1000 – $3FFF)
RAM[15:11] — Internal RAM map position
This register initializes the internal RAM position. Only the upper two
bits define the 16K page the RAM resides in. Bits 13–11 can be
written and read, but are ignored in determining the RAM position.
RAMHAL — Internal RAM map alignment
This register initializes the internal RAM alignment within the 16K
page.
1 = The 12K RAM is aligned to the top of the 16K page ($FFFF)
0 = The 12K RAM is aligned to the bottom of the 16K page ($0000)
EEPROM Mapping The MC9S12DP256 has 4K bytes of EEPROM which is activated by the
EEON bit in the INITEE register. Mapping of internal EEPROM is
controlled by four bits in the INITEE register. After reset EEPROM
address space begins at location $0000 but can be mapped to any 4K
byte boundary within the standard 64K byte address space.
This register initializes the internal EEPROM position.
Normal and Emulation: Write once, except for the EEON bit which can
be written anytime.
Special: Write anytime
NOTE: Writes to this register take one cycle to go into effect.
Read: Anytime.
Reset: $01 (EEPROM located from $0000 – $0FFF)
INITRM — Initialization of Internal RAM Position Register
Address Offset: $0010
Bit 7 654321Bit 0
RAM15 RAM14 RAM13 RAM12 RAM11 0 0 RAMHAL
Reset:
00001001
Freescale Semiconductor, I
Freescale Semiconductor, Inc.
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