Datasheet

Chapter 6 Parallel Input/Output Control
MC9S08SH32 Series Data Sheet, Rev. 2
Freescale Semiconductor 83
6.6.1.4 Port A Slew Rate Enable Register (PTASE)
6.6.1.5 Port A Drive Strength Selection Register (PTADS)
76543210
R
PTASE7 PTASE6 R PTASE4 PTASE3 PTASE2 PTASE1 PTASE0
W
Reset: 00000000
Figure 6-6. Slew Rate Enable for Port A Register (PTASE)
Table 6-5. PTASE Register Field Descriptions
Field Description
7:6,4:0
PTASE
[7:6, 4:0]
Output Slew Rate Enable for Port A Bits — Each of these control bits determines if the output slew rate control
is enabled for the associated PTA pin. For port A pins that are configured as inputs, these bits have no effect.
0 Output slew rate control disabled for port A bit n.
1 Output slew rate control enabled for port A bit n.
5
Reserved
Reserved Bits — These bits are unused on this MCU, writes have no affect and could read as 1s or 0s.
76543210
R
PTADS7 PTADS6 R PTADS4 PTADS3 PTADS2 PTADS1 PTADS0
W
Reset: 00000000
Figure 6-7. Drive Strength Selection for Port A Register (PTADS)
Table 6-6. PTADS Register Field Descriptions
Field Description
7:6, 4:0
PTADS
[7:6, 4:0]
Output Drive Strength Selection for Port A Bits — Each of these control bits selects between low and high
output drive for the associated PTA pin. For port A pins that are configured as inputs, these bits have no effect.
0 Low output drive strength selected for port A bit n.
1 High output drive strength selected for port A bit n.
5
Reserved
Reserved Bits — These bits are unused on this MCU, writes have no affect and could read as 1s or 0s.
PRELIMINARY