Datasheet

Appendix A Electrical Characteristics
MC9S08SH32 Series Data Sheet, Rev. 2
306 Freescale Semiconductor
A.12 AC Characteristics
This section describes ac timing characteristics for each peripheral system.
A.12.1 Control Timing
Figure A-10. Reset Timing
Table A-13. Control Timing
Num C Rating Symbol Min Typ
1
1
Typical values are based on characterization data at V
DD
= 5.0V, 25°C unless otherwise stated.
Max Unit
1D
Bus frequency (t
cyc
= 1/f
Bus
)f
Bus
dc — 20 MHz
2 D Internal low power oscillator period
t
LPO
800 1500 μs
3D
External reset pulse width
2
2
This is the shortest pulse that is guaranteed to be recognized as a reset pin request.
t
extrst
100 — ns
4D
Reset low drive
3
3
When any reset is initiated, internal circuitry drives the reset pin low for about 66 cycles of t
cyc
. After POR reset, the bus clock
frequency changes to the untrimmed DCO frequency (f
reset
= (f
dco_ut
)/4) because TRIM is reset to 0x80 and FTRIM is reset
to 0, and there is an extra divide-by-two because BDIV is reset to 0:1. After other resets trim stays at the pre-reset value.
t
rstdrv
66 x t
cyc
—ns
5D
IRQ pulse width
Asynchronous path
2
Synchronous path
4
t
ILIH,
t
IHIL
100
1.5 x t
cyc
——ns
6D
Pin interrupt pulse width
Asynchronous path
2
Synchronous path
4
4
This is the minimum pulse width that is guaranteed to pass through the pin synchronization circuitry. Shorter pulses may or
may not be recognized. In stop mode, the synchronizer is bypassed so shorter pulses can be recognized in that case.
t
ILIH,
t
IHIL
100
1.5 x t
cyc
——ns
7
C
Port rise and fall time —
Low output drive (PTxDS = 0) (load = 50 pF)
5
Slew rate control disabled (PTxSE = 0)
Slew rate control enabled (PTxSE = 1)
5
Timing is shown with respect to 20% V
DD
and 80% V
DD
levels. Temperature range –40°C to 125°C.
t
Rise
, t
Fall
—
—
40
75
—
—
ns
Port rise and fall time —
High output drive (PTxDS = 1) (load = 50 pF)
5
Slew rate control disabled (PTxSE = 0)
Slew rate control enabled (PTxSE = 1)
t
Rise
, t
Fall
—
—
11
35
—
—
ns
t
extrst
RESET PIN
PRELIMINARY