Datasheet

Appendix A Electrical Characteristics
MC9S08SH32 Series Data Sheet, Rev. 2
Freescale Semiconductor 301
A.9 Internal Clock Source (ICS) Characteristics
Table A-9. ICS Frequency Specifications (Temperature Range = –40 to 125°C Ambient)
Num C Rating Symbol Min Typical Max Unit
1P
Internal reference frequency — factory trimmed at V
DD
= 5 V and temperature = 25°C
f
int_ft
— 31.25 — kHz
2T
Internal reference frequency — untrimmed
1
1
TRIM register at default value (0x80) and FTRIM control bit at default value (0x0).
f
int_ut
25 36 41.66 kHz
3 P Internal reference frequency — trimmed
f
int_t
31.25 — 39.0625 kHz
4 D Internal reference startup time
t
irefst
— 55 100 μs
5—
DCO output frequency range — untrimmed
1
value
provided for reference: f
dco_ut
= 1024 x f
int_ut
f
dco_ut
25.6 36.86 42.66 MHz
6 D DCO output frequency range — trimmed
f
dco_t
32 — 40 MHz
7D
Resolution of trimmed DCO output frequency at fixed
voltage and temperature (using FTRIM)
Δf
dco_res_t
— ± 0.1 ± 0.2
%f
dco
8D
Resolution of trimmed DCO output frequency at fixed
voltage and temperature (not using FTRIM)
Δf
dco_res_t
— ± 0.2 ± 0.4
%f
dco
9D
Total deviation of trimmed DCO output frequency over
voltage and temperature
Δf
dco_t
—
+ 0.5
– 1.0
± 2
%f
dco
10 D
Total deviation of trimmed DCO output frequency over
fixed voltage and temperature range of 0°C to 70 °C
Δf
dco_t
— ± 0.5 ± 1
%f
dco
11 D
FLL acquisition time
2
2
This specification applies to any time the FLL reference source or reference divider is changed, trim value changed or changing
from FLL disabled (FBELP, FBILP) to FLL enabled (FEI, FEE, FBE, FBI). If a crystal/resonator is being used as the reference,
this specification assumes it is already running.
t
acquire
1ms
12 D
DCO output clock long term jitter (over 2 ms interval)
3
3
Jitter is the average deviation from the programmed frequency measured over the specified interval at maximum f
BUS
.
Measurements are made with the device powered by filtered supplies and clocked by a stable external clock signal. Noise
injected into the FLL circuitry via V
DD
and V
SS
and variation in crystal oscillator frequency increase the C
Jitter
percentage for a
given interval.
C
Jitter
— 0.02 0.2
%f
dco
PRELIMINARY