Datasheet

Chapter 2 Pins and Connections
MC9S08SH32 Series Data Sheet, Rev. 2
Freescale Semiconductor 29
Pin Number
Priority
28-pin 20-pin 16-pin Port Pin Alt 1 Alt 2 Alt 3 Alt 4 Alt5
1 — — PTC5 ADP13
2 — — PTC4 ADP12
3 1 1 PTA5 IRQ TCLK
RESET
1
1
Pin does not contain a clamp diode to V
DD
and should not be driven above V
DD
. The voltage measured on
the internally pulled up
RESET in will not be pulled to V
DD
. The internal gates connected to this pin are
pulled to V
DD
.
4 2 2 PTA4 ACMPO BKGD MS
5
33
V
DD
6 V
DDA
V
REFH
7
44
V
SSA
V
REFL
8 V
SS
9 5 5 PTB7 SCL
2
2
IIC pins can be repositioned using IICPS in SOPT2, default reset locations are PTA2, PTA3.
EXTAL
10 6 6 PTB6 SDA
2
XTAL
11 7 7 PTB5 TPM1CH1
3
3
TPM1CHx pins can be repositioned using T1CHxPS bits in SOPT2, default reset locations are PTA0, PTB5.
SS PTC0
4
4
This port pin is part of the ganged output feature. When pin is enabled for ganged output, it will have priority
over all digital modules. The output data, drive strength and slew-rate control of this port pin will follow the
configuration for the PTC0 pin, even in 16-pin packages where PTC0 doesn’t bond out.
12 8 8 PTB4 TPM2CH1
5
5
TPM2CHx pins can be repositioned using T2CHxPS bits in SOPT2, default reset locations are PTA1, PTB4.
MISO PTC0
4
13 9 — PTC3 PTC0
4
ADP11
14 10 — PTC2 PTC0
4
ADP10
15 11 — PTC1 TPM1CH1
3
PTC0
4
ADP9
16 12 — PTC0 TPM1CH0
3
PTC0
4
ADP8
17 13 9 PTB3 PIB3 MOSI PTC0
4
ADP7
18 14 10 PTB2 PIB2 SPSCK PTC0
4
ADP6
19 15 11 PTB1 PIB1 TxD ADP5
20 16 12 PTB0 PIB0 RxD ADP4
21 — — PTA7 TPM2CH1
5
22 — — PTA6 TPM2CH0
5
23 17 13 PTA3 PIA3 SCL
2
ADP3
24 18 14 PTA2 PIA2 SDA
2
ADP2
25 19 15 PTA1 PIA1 TPM2CH0
5
ADP1
6
ACMP-
6
26 20 16 PTA0 PIA0 TPM1CH0
3
ADP0
6
ACMP+
6
27 — — PTC7 ADP15
28 — — PTC6 ADP14
6
If ACMP and ADC are both enabled, both will have access to the pin.
Lowest Highest
Table 2-1. Pin Availability by Package Pin-Count
PRELIMINARY