MC9S08SH32 MC9S08SH16 Data Sheet HCS08 Microcontrollers MC9S08SH32 Rev. 2 4/2008 freescale.
PRELIMINARY
MC9S08SH32 Series Features 8-Bit HCS08 Central Processor Unit (CPU) • 40-MHz HCS08 CPU (central processor unit) • HC08 instruction set with added BGND instruction • Support for up to 32 interrupt/reset sources On-Chip Memory • FLASH read/program/erase over full operating voltage and temperature • Random-access memory (RAM) • Security circuitry to prevent unauthorized access to RAM and FLASH contents Power-Saving Modes • Two very low power stop modes • Reduced power wait mode • Very low power real time cou
PRELIMINARY
MC9S08SH32 Data Sheet Covers MC9S08SH32 MC9S08SH16 MC9S08SH32 Rev. 2 4/2008 Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. © Freescale Semiconductor, Inc., 2007-2008. All rights reserved.
Revision History To provide the most up-to-date information, the revision of our documents on the World Wide Web will be the most current. Your printed copy may be an earlier revision. To verify you have the latest information available, refer to: http://freescale.com/ The following revision history table summarizes changes contained in this document. Revision Number Revision Date 1 10/2007 Updated The ACMP and TPM modules to version 3 and made numerous revisions to the Electricals.
List of Chapters Chapter 1 Device Overview ...................................................................... 19 Chapter 2 Pins and Connections ............................................................. 23 Chapter 3 Modes of Operation ................................................................. 31 Chapter 4 Memory ..................................................................................... 37 Chapter 5 Resets, Interrupts, and General System Control..................
PRELIMINARY
Contents Section Number Title Page Chapter 1 Device Overview 1.1 1.2 1.3 Devices in the MC9S08SH32 Series............................................................................................... 19 MCU Block Diagram ...................................................................................................................... 20 System Clock Distribution ..............................................................................................................
Section Number 4.6 4.7 Title Page 4.5.3 Program and Erase Command Execution ......................................................................... 48 4.5.4 Burst Program Execution.................................................................................................. 49 4.5.5 Access Errors .................................................................................................................... 51 4.5.6 FLASH Block Protection........................................................
Section Number 6.3 6.4 6.5 6.6 Title Page Ganged Output ................................................................................................................................ 77 Pin Interrupts ................................................................................................................................... 78 6.4.1 Edge-Only Sensitivity ....................................................................................................... 78 6.4.2 Edge and Level Sensitivity...
Section Number 8.2 8.3 8.4 8.5 8.6 8.7 Title Page Features ......................................................................................................................................... 115 Modes of Operation....................................................................................................................... 115 Block Diagram ..............................................................................................................................
Section Number 9.5 9.6 Title Page 9.4.7 MCU Stop3 Mode Operation.......................................................................................... 140 9.4.8 MCU Stop1 and Stop2 Mode Operation......................................................................... 141 Initialization Information .............................................................................................................. 141 9.5.1 ADC Module Initialization Example .................................................
Section Number Title Page 11.1.4 Modes of Operation ........................................................................................................ 172 11.2 External Signal Description .......................................................................................................... 173 11.3 Register Definition ........................................................................................................................ 173 11.3.1 ICS Control Register 1 (ICSC1) ................
Section Number Title Page 13.3.3 RTC Modulo Register (RTCMOD) ................................................................................ 198 13.4 Functional Description .................................................................................................................. 198 13.4.1 RTC Operation Example................................................................................................. 199 13.5 Initialization/Application Information .........................................
Section Number Title Page 15.4.3 SPI Baud Rate Register (SPIxBR).................................................................................. 231 15.4.4 SPI Status Register (SPIxS) ............................................................................................ 232 15.4.5 SPI Data Register (SPIxD).............................................................................................. 233 15.5 Functional Description ...................................................................
Section Number Title Page 17.2.2 Communication Details .................................................................................................. 268 17.2.3 BDC Commands ............................................................................................................. 272 17.2.4 BDC Hardware Breakpoint............................................................................................. 274 17.3 On-Chip Debug System (DBG) .........................................................
PRELIMINARY
Chapter 1 Device Overview The MC9S08SH32 members of the low-cost, high-performance HCS08 Family of 8-bit microcontroller units (MCUs). All MCUs in the family use the enhanced HCS08 core and are available with a variety of modules, memory sizes, memory types, and package types. 1.1 Devices in the MC9S08SH32 Series Table 1-1 summarizes the feature set available in the MC9S08SH32 series of MCUs. t Table 1-1.
Chapter 1 Device Overview 1.2 MCU Block Diagram The block diagram in Figure 1-1 shows the structure of the MC9S08SH32 Series MCU.
Chapter 1 Device Overview Table 1-2 provides the functional version of the on-chip modules Table 1-2.
Chapter 1 Device Overview 1.3 System Clock Distribution Figure 1-2 shows a simplified clock connection diagram. Some modules in the MCU have selectable clock inputs as shown. The clock inputs to the modules indicate the clock(s) that are used to drive the module function. The following defines the clocks used in this MCU: • BUSCLK — The frequency of the bus is always half of ICSOUT. • ICSOUT — Primary output of the ICS and is twice the bus frequency.
Chapter 2 Pins and Connections This section describes signals that connect to package pins. It includes pinout diagrams, recommended system connections, and detailed discussions of signals. 2.1 Device Pin Assignment Figure 2-1 - Figure 2-3 shows the pin assignments for the MC9S08SH32 Series devices.
Chapter 2 Pins and Connections PTA5/IRQ/TCLK/RESET PTA4/ACMPO/BKGD/MS VDD VSS PTB7/SCL/EXTAL PTB6/SDA/XTAL PTB5/TPM1CH1/SS PTB4/TPM2CH1/MISO 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 PTA0/PIA0/TPM1CH0/ADP0/ACMP+ PTA1/PIA1/TPM2CH0/ADP1/ACMP– PTA2/PIA2/SDA/ADP2 PTA3/PIA3/SCL/ADP3 PTB0/PIB0/RxD/ADP4 PTB1/PIB1/TxD/ADP5 PTB2/PIB2/SPSCK/ADP6 PTB3/PIB3/MOSI/ADP7 Figure 2-3. 16-Pin TSSOP MC9S08SH32 Series Data Sheet, Rev.
Chapter 2 Pins and Connections 2.2 Recommended System Connections Figure 2-4 shows pin connections that are common to MC9S08SH32 Series application systems. MC9S08SH32 BACKGROUND HEADER PTA0/PIA0/TPM1CH0/ADP0/ACMP+ BKGD/MS VDD PTA1/PIA1/TPM2CH0/ADP1/ACMP– VDD PTA2/PIA2/SDA/ADP2 PORT A 4.7 kΩ–10 kΩ PTA3/PIA3/SCL/ADP3 PTA4/ACMPO/BKGD/MS PTA5/IRQ/TCLK/RESET PTA6/TPM2CH0 PTA7/TPM2CH1 RESET 0.
Chapter 2 Pins and Connections 2.2.1 Power VDD and VSS are the primary power supply pins for the MCU. This voltage source supplies power to all I/O buffer circuitry and to an internal voltage regulator. The internal voltage regulator provides regulated lower-voltage source to the CPU and other internal circuitry of the MCU. Typically, application systems have two separate capacitors across the power pins.
Chapter 2 Pins and Connections 2.2.3 RESET After a power-on reset (POR), the PTA5/IRQ/TCLK/RESET pin defaults to a general-purpose I/O port pin, PTA5. Setting RSTPE in SOPT1 configures the pin to be the RESET pin with an open-drain drive containing an internal pull-up device. After configured as RESET, the pin will remain RESET until the next POR. The RESET pin when enabled can be used to reset the MCU from an external source when the pin is driven low.
Chapter 2 Pins and Connections The BKGD pin is used primarily for background debug controller (BDC) communications using a custom protocol that uses 16 clock cycles of the target MCU’s BDC clock per bit time. The target MCU’s BDC clock could be as fast as the maximum bus clock rate, so there must never be any significant capacitance connected to the BKGD/MS pin that could interfere with background serial communications.
Chapter 2 Pins and Connections Table 2-1.
Chapter 2 Pins and Connections MC9S08SH32 Series Data Sheet, Rev.
Chapter 3 Modes of Operation 3.1 Introduction The operating modes of the MC9S08SH32 Series are described in this chapter. Entry into each mode, exit from each mode, and functionality while in each of the modes are described. 3.2 • • • 3.
Chapter 3 Modes of Operation Background commands are of two types: • Non-intrusive commands, defined as commands that can be issued while the user program is running. Non-intrusive commands can be issued through the BKGD/MS pin while the MCU is in run mode; non-intrusive commands can also be executed when the MCU is in the active background mode.
Chapter 3 Modes of Operation Table 3-1 shows all of the control bits that affect stop mode selection and the mode selected under various conditions. The selected mode is entered following the execution of a STOP instruction. Table 3-1.
Chapter 3 Modes of Operation Most background commands are not available in stop mode. The memory-access-with-status commands do not allow memory access, but they report an error indicating that the MCU is in either stop or wait mode. The BACKGROUND command can be used to wake the MCU from stop and enter active background mode if the ENBDM bit is set. After entering background debug mode, all background commands are available. 3.6.
Chapter 3 Modes of Operation Table 3-2.
Chapter 3 Modes of Operation MC9S08SH32 Series Data Sheet, Rev.
Chapter 4 Memory 4.1 MC9S08SH32 Series Memory Map As shown in Figure 4-1, on-chip memory in the MC9S08SH32 Series series of MCUs consists of RAM, FLASH program memory for nonvolatile data storage, and I/O and control/status registers.
Chapter 4 Memory 4.2 Reset and Interrupt Vector Assignments Table 4-1 shows address assignments for reset and interrupt vectors. The vector names shown in this table are the labels used in the Freescale Semiconductor provided equate file for the MC9S08SH32 Series. Table 4-1.
Chapter 4 Memory 4.3 Register Addresses and Bit Assignments The registers in the MC9S08SH32 Series are divided into these groups: • Direct-page registers are located in the first 128 locations in the memory map; these are accessible with efficient direct addressing mode instructions. • High-page registers are used much less often, so they are located above 0x1800 in the memory map. This leaves more room in the direct page for more frequently used registers and RAM.
Chapter 4 Memory Table 4-2.
Chapter 4 Memory Table 4-2.
Chapter 4 Memory Table 4-2.
Chapter 4 Memory High-page registers, shown in Table 4-3, are accessed much less often than other I/O and control registers so they have been located outside the direct addressable memory space, starting at 0x1800. Table 4-3.
Chapter 4 Memory Table 4-3.
Chapter 4 Memory Nonvolatile FLASH registers, shown in Table 4-4, are located in the FLASH memory. These registers include an 8-byte backdoor key, NVBACKKEY, which can be used to gain access to secure memory resources. During reset events, the contents of NVPROT and NVOPT in the nonvolatile register area of the FLASH memory are transferred into corresponding FPROT and FOPT working registers in the high-page registers to control security and block protection options. Table 4-4.
Chapter 4 Memory 4.4 RAM The MC9S08SH32 Series includes static RAM. The locations in RAM below 0x0100 can be accessed using the more efficient direct addressing mode, and any single bit in this area can be accessed with the bit manipulation instructions (BCLR, BSET, BRCLR, and BRSET). Locating the most frequently accessed program variables in this area of RAM is preferred. The RAM retains data when the MCU is in low-power wait, stop2, or stop3 mode. At power-on the contents of RAM are uninitialized.
Chapter 4 Memory 4.5.1 Features Features of the FLASH memory include: • FLASH size — MC9S08SH32: 32,768 bytes (64 pages of 512 bytes each) — MC9S08SH16: 16,384 bytes (32 pages of 512 bytes each) • Single power supply program and erase • Command interface for fast program and erase operation • Up to 100,000 program/erase cycles at typical voltage and temperature • Flexible block protection and vector redirection • Security feature for FLASH and RAM • Auto power-down for low-frequency read accesses 4.5.
Chapter 4 Memory 4.5.3 Program and Erase Command Execution The steps for executing any of the commands are listed below. The FCDIV register must be initialized and any error flags cleared before beginning command execution. The command execution steps are: 1. Write a data value to an address in the FLASH array. The address and data information from this write is latched into the FLASH interface. This write is a required first step in any command sequence.
Chapter 4 Memory Note 1: Required only once after reset. WRITE TO FCDIV (Note 1) FLASH PROGRAM AND ERASE FLOW START FACCERR ? 0 1 CLEAR ERROR WRITE TO FLASH TO BUFFER ADDRESS AND DATA WRITE COMMAND TO FCMD WRITE 1 TO FCBEF TO LAUNCH COMMAND AND CLEAR FCBEF (Note 2) FPVIOL OR FACCERR ? Note 2: Wait at least four bus cycles before checking FCBEF or FCCF. YES ERROR EXIT NO 0 FCCF ? 1 DONE Figure 4-2. FLASH Program and Erase Flowchart 4.5.
Chapter 4 Memory The first byte of a series of sequential bytes being programmed in burst mode will take the same amount of time to program as a byte programmed in standard mode. Subsequent bytes will program in the burst program time provided that the conditions above are met. In the case the next sequential address is the beginning of a new row, the program time for that byte will be the standard time instead of the burst time.
Chapter 4 Memory 4.5.5 Access Errors An access error occurs whenever the command execution protocol is violated. Any of the following specific actions will cause the access error flag (FACCERR) in FSTAT to be set. FACCERR must be cleared by writing a 1 to FACCERR in FSTAT before any command can be processed.
Chapter 4 Memory be programmed to logic 0 to enable block protection. Therefore the value 0xF8 must be programmed into NVPROT to protect addresses 0xFA00 through 0xFFFF. FPS7 FPS6 FPS5 FPS4 FPS3 FPS2 FPS1 A15 A14 A13 A12 A11 A10 A9 1 1 1 1 1 1 1 1 1 A8 A7 A6 A5 A4 A3 A2 A1 A0 Figure 4-4. Block Protection Mechanism One use for block protection is to block protect an area of FLASH memory for a bootloader program.
Chapter 4 Memory the MCU secure. During development, whenever the FLASH is erased, it is good practice to immediately program the SEC00 bit to 0 in NVOPT so SEC01:SEC00 = 1:0. This would allow the MCU to remain unsecured after a subsequent reset. The on-chip debug module cannot be enabled while the MCU is secure. The separate background debug controller can still be used for background memory access commands of unsecured resources.
Chapter 4 Memory control registers (FOPT, FPROT) at reset. There is also an 8-byte comparison key in FLASH memory. Refer to Table 4-3 and Table 4-4 for the absolute address assignments for all FLASH registers. This section refers to registers and control bits only by their names. A Freescale Semiconductor-provided equate or header file normally is used to translate these names into the appropriate absolute addresses. 4.7.1 FLASH Clock Divider Register (FCDIV) Bit 7 of this register is a read-only flag.
Chapter 4 Memory Table 4-7. FLASH Clock Divider Settings 4.7.2 fBus PRDIV8 (Binary) DIV (Decimal) fFCLK Program/Erase Timing Pulse (5 μs Min, 6.7 μs Max) 20 MHz 1 12 192.3 kHz 5.2 μs 10 MHz 0 49 200 kHz 5 μs 8 MHz 0 39 200 kHz 5 μs 4 MHz 0 19 200 kHz 5 μs 2 MHz 0 9 200 kHz 5 μs 1 MHz 0 4 200 kHz 5 μs 200 kHz 0 0 200 kHz 5 μs 150 kHz 0 0 150 kHz 6.
Chapter 4 Memory Table 4-9. Security States1 1 4.7.3 R SEC01:SEC00 Description 0:0 secure 0:1 secure 1:0 unsecured 1:1 secure SEC01:SEC00 changes to 1:0 after successful backdoor key entry or a successful blank check of FLASH. FLASH Configuration Register (FCNFG) 7 6 0 0 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 KEYACC W Reset 0 0 0 = Unimplemented or Reserved Figure 4-7. FLASH Configuration Register (FCNFG) Table 4-10.
Chapter 4 Memory Table 4-11. FPROT Register Field Descriptions Field Description 7:1 FPS FLASH Protect Select Bits — When FPDIS = 0, this 7-bit field determines the ending address of unprotected FLASH locations at the high address end of the FLASH. Protected FLASH locations cannot be erased or programmed. 0 FPDIS 4.7.5 FLASH Protection Disable 0 FLASH block specified by [7:1] is block protected (program and erase not allowed). 1 No FLASH block is protected.
Chapter 4 Memory Table 4-12. FSTAT Register Field Descriptions (continued) Field Description 4 FACCERR Access Error Flag — FACCERR is set automatically when the proper command sequence is not obeyed exactly (the erroneous command is ignored), if a program or erase operation is attempted before the FCDIV register has been initialized, or if the MCU enters stop while a command was in progress. For a more detailed discussion of the exact actions that are considered access errors, see Section 4.5.
Chapter 5 Resets, Interrupts, and General System Control 5.1 Introduction This section discusses basic reset and interrupt mechanisms and the various sources of reset and interrupt in the MC9S08SH32 Series. Some interrupt sources from peripheral modules are discussed in greater detail within other sections of this data sheet. This section gathers basic information about all reset and interrupt sources in one place for easy reference.
Chapter 5 Resets, Interrupts, and General System Control 5.4 Computer Operating Properly (COP) Watchdog The COP watchdog is intended to force a system reset when the application software fails to execute as expected. To prevent a system reset from the COP timer (when it is enabled), application software must reset the COP counter periodically.
Chapter 5 Resets, Interrupts, and General System Control The COP counter is initialized by the first writes to the SOPT1 and SOPT2 registers after any system reset. Subsequent writes to SOPT1 and SOPT2 have no effect on COP operation. Even if the application will use the reset default settings of COPT, COPCLKS, and COPW bits, the user should write to the write-once SOPT1 and SOPT2 registers during reset initialization to lock in the settings.
Chapter 5 Resets, Interrupts, and General System Control other than the most experienced programmers because it can lead to subtle program errors that are difficult to debug. The interrupt service routine ends with a return-from-interrupt (RTI) instruction which restores the CCR, A, X, and PC registers to their pre-interrupt values by reading the previously saved information from the stack. NOTE For compatibility with M68HC08 devices, the H register is not automatically saved and restored.
Chapter 5 Resets, Interrupts, and General System Control The status flag corresponding to the interrupt source must be acknowledged (cleared) before returning from the ISR. Typically, the flag is cleared at the beginning of the ISR so that if another interrupt is generated by this same source, it will be registered so it can be serviced after completion of the current ISR. 5.5.2 External Interrupt Request Pin (IRQ) External interrupts are managed by the IRQ status and control register, IRQSC.
Chapter 5 Resets, Interrupts, and General System Control When an interrupt condition occurs, an associated flag bit becomes set. If the associated local interrupt enable is 1, an interrupt request is sent to the CPU. Within the CPU, if the global interrupt mask (I bit in the CCR) is 0, the CPU will finish the current instruction; stack the PCL, PCH, X, A, and CCR CPU registers; set the I bit; and then fetch the interrupt vector for the highest priority pending interrupt.
Chapter 5 Resets, Interrupts, and General System Control 5.6 Low-Voltage Detect (LVD) System The MC9S08SH32 Series includes a system to protect against low voltage conditions in order to protect memory contents and control MCU system states during supply voltage variations. The system is comprised of a power-on reset (POR) circuit and a LVD circuit with trip voltages for warning and detection. The LVD circuit is enabled when LVDE in SPMSC1 is set to 1.
Chapter 5 Resets, Interrupts, and General System Control 5.7.1 Interrupt Pin Request Status and Control Register (IRQSC) This direct page register includes status and control bits, which are used to configure the IRQ function, report status, and acknowledge IRQ events. 7 R 6 5 4 IRQPDD IRQEDG IRQPE 0 3 2 IRQF 0 W Reset 1 0 IRQIE IRQMOD 0 0 IRQACK 0 0 0 0 0 0 = Unimplemented or Reserved Figure 5-2. Interrupt Request Status and Control Register (IRQSC) Table 5-3.
Chapter 5 Resets, Interrupts, and General System Control 5.7.2 System Reset Status Register (SRS) This high page register includes read-only status flags to indicate the source of the most recent reset. When a debug host forces reset by writing 1 to BDFR in the SBDFR register, none of the status bits in SRS will be set. Writing any value to this register address causes a COP reset when the COP is enabled except the values 0x55 and 0xAA.
Chapter 5 Resets, Interrupts, and General System Control Table 5-4. SRS Register Field Descriptions Field Description 3 ILAD Illegal Address — Reset was caused by an attempt to access either data or an instruction at an unimplemented memory address. 0 Reset not caused by an illegal address 1 Reset caused by an illegal address 1 LVD Low Voltage Detect — If the LVDRE bit is set and the supply drops below the LVD trip voltage, an LVD reset will occur. This bit is also set by POR.
Chapter 5 Resets, Interrupts, and General System Control 5.7.4 System Options Register 1 (SOPT1) This high page register is a write-once register so only the first write after reset is honored. It can be read at any time. Any subsequent attempt to write to SOPT1 (intentionally or unintentionally) is ignored to avoid accidental changes to these sensitive settings.
Chapter 5 Resets, Interrupts, and General System Control 5.7.5 System Options Register 2 (SOPT2) This high page register contains bits to configure MCU specific features on the MC9S08SH32 Series devices. R 7 6 5 COPCLKS1 COPW1 0 0 4 3 2 1 0 ACIC T2CH1PS T2CH0PS T1CH1PS T1CH0PS 0 0 0 0 0 0 W Reset: 0 = Unimplemented or Reserved Figure 5-6. System Options Register 2 (SOPT2) 1 This bit can be written only one time after reset. Additional writes are ignored. Table 5-7.
Chapter 5 Resets, Interrupts, and General System Control 5.7.6 System Device Identification Register (SDIDH, SDIDL) These high page read-only registers are included so host development systems can identify the HCS08 derivative and revision number. This allows the development software to recognize where specific memory blocks, registers, and control bits are located in a target MCU.
Chapter 5 Resets, Interrupts, and General System Control 5.7.7 System Power Management Status and Control 1 Register (SPMSC1) This high page register contains status and control bits to support the low voltage detect function, and to enable the bandgap voltage reference for use by the ADC module. This register should be written during the user’s reset initialization program to set the desired controls even if the desired settings are the same as the reset settings.
Chapter 5 Resets, Interrupts, and General System Control 5.7.8 System Power Management Status and Control 2 Register (SPMSC2) This register is used to report the status of the low voltage warning function, and to configure the stop mode behavior of the MCU.
Chapter 5 Resets, Interrupts, and General System Control Table 5-12. LVD and LVW trip point typical values1 1 LVDV:LVWV LVW Trip Point LVD Trip Point 0:0 VLVW0 = 2.74 V VLVD0 = 2.56 V 0:1 VLVW1 = 2.92 V 1:0 VLVW2 = 4.3 V 1:1 VLVW3 = 4.6 V VLVD1 = 4.0 V See Electrical Characteristics appendix for minimum and maximum values. MC9S08SH32 Series Data Sheet, Rev.
Chapter 6 Parallel Input/Output Control This section explains software controls related to parallel input/output (I/O) and pin control. The MC9S08SH32 has three parallel I/O ports which include a total of 23 I/O pins and one output-only pin. See Chapter 2, “Pins and Connections,” for more information about pin assignments and external hardware considerations of these pins.
Chapter 6 Parallel Input/Output Control It is a good programming practice to write to the port data register before changing the direction of a port pin to become an output. This ensures that the pin will not be driven momentarily with an old data value that happened to be in the port data register. PTxDDn D Output Enable Q PTxDn D Output Data Q 1 Port Read Data 0 Synchronizer Input Data BUSCLK Figure 6-1. Parallel I/O Block Diagram 6.
Chapter 6 Parallel Input/Output Control 6.3 Ganged Output The MC9S08SH32 Series devices contain a feature that allows for up to eight port pins to be tied together externally to allow higher output current drive. The ganged output drive control register (GNGC) is a write-once register that is used to enabled the ganged output feature and select which port pins will be used as ganged outputs. The GNGEN bit in GNGC enables ganged output.
Chapter 6 Parallel Input/Output Control 6.4 Pin Interrupts Port A[3:0] and port B[3:0] pins can be configured as external interrupt inputs and as an external means of waking the MCU from stop3 or wait low-power modes. The block diagram for the pin interrupts is shown Figure 6-2. BUSCLK PTxACK VDD 1 PIxn 0 S RESET PTxIF D CLR Q PTxPS0 SYNCHRONIZER CK PTxES0 PORT INTERRUPT FF 1 PIxn 0 S STOP STOP BYPASS PTx INTERRUPT REQUEST PTxMOD PTxPSn PTxIE PTxESn Figure 6-2.
Chapter 6 Parallel Input/Output Control 6.4.2 Edge and Level Sensitivity A valid edge or level on an enabled pin interrupt sets PTxIF in PTxSC. If PTxIE in PTxSC is set, an interrupt request is presented to the CPU. To clear PTxIF, write a 1 to PTxACK in PTxSC provided all enabled pin interrupt inputs are at their de-asserted levels. PTxIF remains set if any enabled pin interrupt is asserted while attempting to clear by writing a 1 to PTxACK. 6.4.
Chapter 6 Parallel Input/Output Control 6.6 Parallel I/O and Pin Control Registers This section provides information about the registers associated with the parallel I/O ports. The data and data direction registers are located in page zero of the memory map. The pull up, slew rate, drive strength, and interrupt control registers are located in the high page section of the memory map.
Chapter 6 Parallel Input/Output Control 6.6.1 Port A Registers Port A is controlled by the registers listed below. The pins PTA4 and PTA5 are unique. PTA4 is output-only, so the control bits for the input function will not have any effect on this pin. PTA5, when configured as an output, is open drain. NOTE This PTA5 pin does not contain a clamp diode to VDD and should not be driven above VDD.
Chapter 6 Parallel Input/Output Control 6.6.1.2 Port A Data Direction Register (PTADD) 7 6 5 4 3 2 1 0 PTADD7 PTADD6 PTADD5 PTADD41 PTADD3 PTADD2 PTADD1 PTADD0 0 0 0 0 0 0 0 0 R W Reset: Figure 6-4. Port A Data Direction Register (PTADD) 1 PTADD4 has no effect on the output-only PTA4 pin. Table 6-3. PTADD Register Field Descriptions Field Description Data Direction for Port A Bits — These read/write bits control the direction of port A pins and what is read for 7:0 PTAD reads.
Chapter 6 Parallel Input/Output Control 6.6.1.4 Port A Slew Rate Enable Register (PTASE) 7 6 5 4 3 2 1 0 PTASE7 PTASE6 R PTASE4 PTASE3 PTASE2 PTASE1 PTASE0 0 0 0 0 0 0 0 0 R W Reset: Figure 6-6. Slew Rate Enable for Port A Register (PTASE) Table 6-5. PTASE Register Field Descriptions Field Description 7:6,4:0 PTASE [7:6, 4:0] Output Slew Rate Enable for Port A Bits — Each of these control bits determines if the output slew rate control is enabled for the associated PTA pin.
Chapter 6 Parallel Input/Output Control 6.6.1.6 R Port A Interrupt Status and Control Register (PTASC) 7 6 5 4 3 2 0 0 0 0 PTAIF 0 W Reset: 1 0 PTAIE PTAMOD 0 0 PTAACK 0 0 0 0 0 0 Figure 6-8. Port A Interrupt Status and Control Register (PTASC) Table 6-7. PTASC Register Field Descriptions Field Description 3 PTAIF Port A Interrupt Flag — PTAIF indicates when a port A interrupt is detected. Writes have no effect on PTAIF. 0 No port A interrupt detected.
Chapter 6 Parallel Input/Output Control 6.6.1.8 R Port A Interrupt Edge Select Register (PTAES) 7 6 5 4 0 0 0 0 3 2 1 0 PTAES3 PTAES2 PTAES1 PTAES0 0 0 0 0 W Reset: 0 0 0 0 Figure 6-10. Port A Edge Select Register (PTAES) Table 6-9.
Chapter 6 Parallel Input/Output Control 6.6.2 Port B Registers Port B is controlled by the registers listed below. 6.6.2.1 Port B Data Register (PTBD) 7 6 5 4 3 2 1 0 PTBD7 PTBD6 PTBD5 PTBD4 PTBD3 PTBD2 PTBD1 PTBD0 0 0 0 0 0 0 0 0 R W Reset: Figure 6-11. Port B Data Register (PTBD) Table 6-10. PTBD Register Field Descriptions Field Description 7:0 PTBD[7:0] Port B Data Register Bits — For port B pins that are inputs, reads return the logic level on the pin.
Chapter 6 Parallel Input/Output Control 6.6.2.3 Port B Pull Enable Register (PTBPE) 7 6 5 4 3 2 1 0 PTBPE7 PTBPE6 PTBPE5 PTBPE4 PTBPE3 PTBPE2 PTBPE1 PTBPE0 0 0 0 0 0 0 0 0 R W Reset: Figure 6-13. Internal Pull Enable for Port B Register (PTBPE) Table 6-12. PTBPE Register Field Descriptions Field Description 7:0 Internal Pull Enable for Port B Bits — Each of these control bits determines if the internal pull-up or pull-down PTBPE[7:0] device is enabled for the associated PTB pin.
Chapter 6 Parallel Input/Output Control 6.6.2.5 Port B Drive Strength Selection Register (PTBDS) 7 6 5 4 3 2 1 0 PTBDS7 PTBDS6 PTBDS5 PTBDS4 PTBDS3 PTBDS2 PTBDS1 PTBDS0 0 0 0 0 0 0 0 0 R W Reset: Figure 6-15. Drive Strength Selection for Port B Register (PTBDS) Table 6-14.
Chapter 6 Parallel Input/Output Control 6.6.2.7 R Port B Interrupt Pin Select Register (PTBPS) 7 6 5 4 0 0 0 0 3 2 1 0 PTBPS3 PTBPS2 PTBPS1 PTBPS0 0 0 0 0 W Reset: 0 0 0 0 Figure 6-17. Port B Interrupt Pin Select Register (PTBPS) Table 6-16. PTBPS Register Field Descriptions Field Description 3:0 Port B Interrupt Pin Selects — Each of the PTBPSn bits enable the corresponding port B interrupt pin. PTBPS[3:0] 0 Pin not enabled as interrupt. 1 Pin enabled as interrupt. 6.6.2.
Chapter 6 Parallel Input/Output Control 6.6.3 Port C Registers Port C is controlled by the registers listed below. 6.6.3.1 Port C Data Register (PTCD) 7 6 5 4 3 2 1 0 PTCD7 PTCD6 PTCD5 PTCD4 PTCD3 PTCD2 PTCD1 PTCD0 0 0 0 0 0 0 0 0 R W Reset: Figure 6-19. Port C Data Register (PTCD) Table 6-18. PTCD Register Field Descriptions Field Description 7:0 PTCD[7:0] Port C Data Register Bits — For port C pins that are inputs, reads return the logic level on the pin.
Chapter 6 Parallel Input/Output Control 6.6.3.3 Port C Pull Enable Register (PTCPE) 7 6 5 4 3 2 1 0 PTCPE7 PTCPE6 PTCPE5 PTCPE4 PTCPE3 PTCPE2 PTCPE1 PTCPE0 0 0 0 0 0 0 0 0 R W Reset: Figure 6-21. Internal Pull Enable for Port C Register (PTCPE) Table 6-20. PTCPE Register Field Descriptions Field Description 7:0 Internal Pull Enable for Port C Bits — Each of these control bits determines if the internal pull-up device is PTCPE[7:0] enabled for the associated PTC pin.
Chapter 6 Parallel Input/Output Control 6.6.3.5 Port C Drive Strength Selection Register (PTCDS) 7 6 5 4 3 2 1 0 PTCDS7 PTCDS6 PTCDS5 PTCDS4 PTCDS3 PTCDS2 PTCDS1 PTCDS0 0 0 0 0 0 0 0 0 R W Reset: Figure 6-23. Drive Strength Selection for Port C Register (PTCDS) Table 6-22.
Chapter 7 Central Processor Unit (S08CPUV3) 7.1 Introduction This section provides summary information about the registers, addressing modes, and instruction set of the CPU of the HCS08 Family. For a more detailed discussion, refer to the HCS08 Family Reference Manual, volume 1, Freescale Semiconductor document order number HCS08RMV1/D. The HCS08 CPU is fully source- and object-code-compatible with the M68HC08 CPU.
Chapter 7 Central Processor Unit (S08CPUV3) 7.2 Programmer’s Model and CPU Registers Figure 7-1 shows the five CPU registers. CPU registers are not part of the memory map. 7 0 ACCUMULATOR A 16-BIT INDEX REGISTER H:X H INDEX REGISTER (HIGH) 8 15 INDEX REGISTER (LOW) X 0 7 SP STACK POINTER 0 15 PROGRAM COUNTER 7 0 CONDITION CODE REGISTER V 1 1 H I N Z C PC CCR CARRY ZERO NEGATIVE INTERRUPT MASK HALF-CARRY (FROM BIT 3) TWO’S COMPLEMENT OVERFLOW Figure 7-1. CPU Registers 7.2.
Chapter 7 Central Processor Unit (S08CPUV3) 7.2.3 Stack Pointer (SP) This 16-bit address pointer register points at the next available location on the automatic last-in-first-out (LIFO) stack. The stack may be located anywhere in the 64-Kbyte address space that has RAM and can be any size up to the amount of available RAM. The stack is used to automatically save the return address for subroutine calls, the return address and CPU registers during interrupts, and for local variables.
Chapter 7 Central Processor Unit (S08CPUV3) 7 0 CONDITION CODE REGISTER V 1 1 H I N Z C CCR CARRY ZERO NEGATIVE INTERRUPT MASK HALF-CARRY (FROM BIT 3) TWO’S COMPLEMENT OVERFLOW Figure 7-2. Condition Code Register Table 7-1. CCR Register Field Descriptions Field Description 7 V Two’s Complement Overflow Flag — The CPU sets the overflow flag when a two’s complement overflow occurs. The signed branch instructions BGT, BGE, BLE, and BLT use the overflow flag.
Chapter 7 Central Processor Unit (S08CPUV3) 7.3 Addressing Modes Addressing modes define the way the CPU accesses operands and data. In the HCS08, all memory, status and control registers, and input/output (I/O) ports share a single 64-Kbyte linear address space so a 16-bit binary address can uniquely identify any memory location. This arrangement means that the same instructions that access variables in RAM can also be used to access I/O and control registers or nonvolatile program space.
Chapter 7 Central Processor Unit (S08CPUV3) 7.3.5 Extended Addressing Mode (EXT) In extended addressing mode, the full 16-bit address of the operand is located in the next two bytes of program memory after the opcode (high byte first). 7.3.6 Indexed Addressing Mode Indexed addressing mode has seven variations including five that use the 16-bit H:X index register pair and two that use the stack pointer as the base reference. 7.3.6.
Chapter 7 Central Processor Unit (S08CPUV3) 7.3.6.7 SP-Relative, 16-Bit Offset (SP2) This variation of indexed addressing uses the 16-bit value in the stack pointer (SP) plus a 16-bit offset included in the instruction as the address of the operand needed to complete the instruction. 7.4 Special Operations The CPU performs a few special operations that are similar to instructions but do not have opcodes like other CPU instructions.
Chapter 7 Central Processor Unit (S08CPUV3) interrupt service routine, this would allow nesting of interrupts (which is not recommended because it leads to programs that are difficult to debug and maintain). For compatibility with the earlier M68HC05 MCUs, the high-order half of the H:X index register pair (H) is not saved on the stack as part of the interrupt sequence.
Chapter 7 Central Processor Unit (S08CPUV3) 7.4.5 BGND Instruction The BGND instruction is new to the HCS08 compared to the M68HC08. BGND would not be used in normal user programs because it forces the CPU to stop processing user instructions and enter the active background mode. The only way to resume execution of the user program is through reset or by a host debug system issuing a GO, TRACE1, or TAGGO serial command through the background debug interface.
Chapter 7 Central Processor Unit (S08CPUV3) 7.5 HCS08 Instruction Set Summary Table 7-2 provides a summary of the HCS08 instruction set in all possible addressing modes. The table shows operand construction, execution time in internal bus clock cycles, and cycle-by-cycle details for each addressing mode variation of each instruction.
Chapter 7 Central Processor Unit (S08CPUV3) Operation Object Code Cycles Source Form Address Mode Table 7-2.
Chapter 7 Central Processor Unit (S08CPUV3) Operation Object Code Cycles Source Form Address Mode Table 7-2.
Chapter 7 Central Processor Unit (S08CPUV3) CMP CMP CMP CMP CMP CMP CMP CMP #opr8i opr8a opr16a oprx16,X oprx8,X ,X oprx16,SP oprx8,SP Operation Compare Accumulator with Memory A–M (CCR Updated But Operands Not Changed) Object Code IMM DIR EXT IX2 IX1 IX SP2 SP1 A1 B1 C1 D1 E1 F1 9E D1 9E E1 ii dd hh ll ee ff ff ee ff ff Cycles Source Form Address Mode Table 7-2.
Chapter 7 Central Processor Unit (S08CPUV3) INC opr8a INCA INCX INC oprx8,X INC ,X INC oprx8,SP Operation Increment M ← (M) + $01 A ← (A) + $01 X ← (X) + $01 M ← (M) + $01 M ← (M) + $01 M ← (M) + $01 Object Code Cycles Source Form Address Mode Table 7-2.
Chapter 7 Central Processor Unit (S08CPUV3) Operation Object Code MOV opr8a,opr8a MOV opr8a,X+ MOV #opr8i,opr8a MOV ,X+,opr8a Move (M)destination ← (M)source In IX+/DIR and DIR/IX+ Modes, H:X ← (H:X) + $0001 DIR/DIR DIR/IX+ IMM/DIR IX+/DIR 4E 5E 6E 7E MUL Unsigned multiply X:A ← (X) × (A) INH NEG opr8a NEGA NEGX NEG oprx8,X NEG ,X NEG oprx8,SP Negate M ← – (M) = $00 – (M) (Two’s Complement) A ← – (A) = $00 – (A) X ← – (X) = $00 – (X) M ← – (M) = $00 – (M) M ← – (M) = $00 – (M) M ← – (M) = $00 – (
Chapter 7 Central Processor Unit (S08CPUV3) Operation Object Code Cycles Source Form Address Mode Table 7-2.
Chapter 7 Central Processor Unit (S08CPUV3) SUB SUB SUB SUB SUB SUB SUB SUB #opr8i opr8a opr16a oprx16,X oprx8,X ,X oprx16,SP oprx8,SP Operation Object Code IMM DIR EXT IX2 IX1 IX SP2 SP1 A0 B0 C0 D0 E0 F0 9E D0 9E E0 SWI Software Interrupt PC ← (PC) + $0001 Push (PCL); SP ← (SP) – $0001 Push (PCH); SP ← (SP) – $0001 Push (X); SP ← (SP) – $0001 Push (A); SP ← (SP) – $0001 Push (CCR); SP ← (SP) – $0001 I ← 1; PCH ← Interrupt Vector High Byte PCL ← Interrupt Vector Low Byte INH TAP Transfer Accumul
Chapter 7 Central Processor Unit (S08CPUV3) Operation Object Code Cycles Source Form Address Mode Table 7-2. Instruction Set Summary (Sheet 9 of 9) Affect on CCR Cyc-by-Cyc Details V11H INZC TXS Transfer Index Reg. to SP SP ← (H:X) – $0001 INH 94 2 fp – 1 1 – – – – – WAIT Enable Interrupts; Wait for Interrupt I bit ← 0; Halt CPU INH 8F 2+ fp...
Chapter 7 Central Processor Unit (S08CPUV3) Table 7-3.
Chapter 7 Central Processor Unit (S08CPUV3) Table 7-3.
Chapter 8 Analog Comparator 5-V (S08ACMPV3) 8.1 Introduction The analog comparator module (ACMP) provides a circuit for comparing two analog input voltages or for comparing one analog input voltage to an internal reference voltage. The comparator circuit is designed to operate across the full range of the supply voltage (rail-to-rail operation). Figure 8-1 shows the MC9S08SH32 Series block diagram with the ACMP highlighted. 8.1.
Chapter 8 Analog Comparator 5-V (S08ACMPV3) BKGD/MS HCS08 CORE DEBUG MODULE (DBG) PTA6/TPM2CH0 HCS08 SYSTEM CONTROL RESETS AND INTERRUPTS MODES OF OPERATION POWER MANAGEMENT IRQ SCL IRQ IIC MODULE (IIC) LVD SERIAL PERIPHERAL INTERFACE MODULE (SPI) USER FLASH (MC9S08SH32 = 32,768 BYTES) (MC9S08SH16 = 16,384 BYTES) SERIAL COMMUNICATIONS INTERFACE MODULE (SCI) PTA5/IRQ/TCLK/RESET 16-BIT TIMER/PWM MODULE (TPM1) REAL-TIME COUNTER (RTC) 40-MHz INTERNAL CLOCK SOURCE (ICS) PTA1/PIA1/TPM2CH0/ADP1/ACMP–
Chapter 8 Analog Comparator (S08ACMPV3) 8.2 Features The ACMP has the following features: • Full rail to rail supply operation. • Selectable interrupt on rising edge, falling edge, or either rising or falling edges of comparator output. • Option to compare to fixed internal bandgap reference voltage. • Option to allow comparator output to be visible on a pin, ACMPO. • Can operate in stop3 mode 8.3 Modes of Operation This section defines the ACMP operation in wait, stop and background debug modes. 8.
Chapter 8 Analog Comparator (S08ACMPV3) Internal Bus Internal Reference ACIE ACBGS ACME ACMP INTERRUPT REQUEST Status & Control Register ACF ACMP+ + Interrupt Control - ACMP- set ACF ACMOD ACOPE Comparator ACMPO Figure 8-2. Analog Comparator 5V (ACMP5) Block Diagram MC9S08SH32 Series Data Sheet, Rev.
Chapter 8 Analog Comparator (S08ACMPV3) 8.5 External Signal Description The ACMP has two analog input pins, ACMP+ and ACMP- and one digital output pin ACMPO. Each of these pins can accept an input voltage that varies across the full operating voltage range of the MCU. As shown in Figure 8-2, the ACMP- pin is connected to the inverting input of the comparator, and the ACMP+ pin is connected to the comparator non-inverting input if ACBGS is a 0.
Chapter 8 Analog Comparator (S08ACMPV3) 8.6.1.1 ACMP Status and Control Register (ACMPSC) ACMPSC contains the status flag and control bits which are used to enable and configure the ACMP. 7 6 5 4 3 ACME ACBGS ACF ACIE 0 0 0 0 R 2 1 0 ACO ACOPE ACMOD W Reset: 0 0 0 0 = Unimplemented Figure 8-3. ACMP Status and Control Register Table 8-2. ACMP Status and Control Register Field Descriptions Field 7 ACME Description Analog Comparator Module Enable — ACME enables the ACMP module.
Chapter 8 Analog Comparator (S08ACMPV3) 8.7 Functional Description The analog comparator can be used to compare two analog input voltages applied to ACMP+ and ACMP-; or it can be used to compare an analog input voltage applied to ACMP- with an internal bandgap reference voltage. ACBGS is used to select between the bandgap reference voltage or the ACMP+ pin as the input to the non-inverting input of the analog comparator.
Chapter 8 Analog Comparator (S08ACMPV3) MC9S08SH32 Series Data Sheet, Rev.
Chapter 9 Analog-to-Digital Converter (S08ADCV1) 9.1 Introduction The 10-bit analog-to-digital converter (ADC) is a successive approximation ADC designed for operation within an integrated microcontroller system-on-chip. NOTE MC9S08SH32 Series devices operate at a higher voltage range (2.7 V to 5.5 V) and do not include stop1 mode. Please ignore references to stop1.
Chapter 9 Analog-to-Digital Converter (S08ADCV1) 2 Requires BGBE =1 in SPMSC1 see Section 5.7.6, “System Power Management Status and Control 1 Register (SPMSC1)”. For value of bandgap voltage reference see A.6, “DC Characteristics”. 9.1.2 Analog Power and Ground Signal Names References to VDDAD and VSSAD in this chapter correspond to signals VDDA and VSSA, respectively. 9.1.
Chapter 9 Analog-to-Digital Converter (S08ADCV1) Equation 9-1 provides an approximate transfer function of the temperature sensor. Temp = 25 - ((VTEMP -VTEMP25) ÷ m) Eqn. 9-1 where: — VTEMP is the voltage of the temperature sensor channel at the ambient temperature. — VTEMP25 is the voltage of the temperature sensor channel at 25°C. — m is the hot or cold voltage versus temperature slope in V/°C. For temperature calculations, use the VTEMP25 and m values from the ADC Electricals table.
Chapter 9 Analog-to-Digital Converter (S08ADCV1) BKGD/MS HCS08 CORE DEBUG MODULE (DBG) PTA6/TPM2CH0 IRQ SCL IRQ IIC MODULE (IIC) LVD SERIAL PERIPHERAL INTERFACE MODULE (SPI) USER FLASH (MC9S08SH32 = 32,768 BYTES) (MC9S08SH16 = 16,384 BYTES) SERIAL COMMUNICATIONS INTERFACE MODULE (SCI) 16-BIT TIMER/PWM MODULE (TPM1) REAL-TIME COUNTER (RTC) 40-MHz INTERNAL CLOCK SOURCE (ICS) PTA1/PIA1/TPM2CH0/ADP1/ACMP– PTA0/PIA0/TPM1CH0/ADP0/ACMP+ SS MISO MOSI SPSCK RxD TxD PTB7/SCL/EXTAL PTB6/SDA/XTAL TCLK T
Chapter 9 Analog-to-Digital Converter (S08ADC10V1) 9.1.6 Features Features of the ADC module include: • Linear successive approximation algorithm with 10 bits resolution. • Up to 28 analog inputs. • Output formatted in 10- or 8-bit right-justified format. • Single or continuous conversion (automatic return to idle after single conversion). • Configurable sample time and conversion speed/power. • Conversion complete flag and interrupt. • Input clock selectable from up to four sources.
Chapter 9 Analog-to-Digital Converter (S08ADC10V1) ADIV ADLPC MODE ADLSMP ADTRG 2 ADCO ADCH 1 ADCCFG complete COCO ADCSC1 ADICLK Compare true AIEN 3 Async Clock Gen ADACK MCU STOP ADCK ÷2 ALTCLK abort transfer sample initialize ••• AD0 convert Control Sequencer ADHWT Bus Clock Clock Divide AIEN 1 Interrupt COCO 2 ADVIN SAR Converter AD27 VREFH Data Registers Sum VREFL Compare true 3 ACFGT Value Compare Logic ADCSC2 Compare Value Registers Figure 9-2.
Chapter 9 Analog-to-Digital Converter (S08ADC10V1) 9.2.1 Analog Power (VDDAD) The ADC analog portion uses VDDAD as its power connection. In some packages, VDDAD is connected internally to VDD. If externally available, connect the VDDAD pin to the same voltage potential as VDD. External filtering may be necessary to ensure clean VDDAD for good results. 9.2.2 Analog Ground (VSSAD) The ADC analog portion uses VSSAD as its ground connection. In some packages, VSSAD is connected internally to VSS.
Chapter 9 Analog-to-Digital Converter (S08ADC10V1) 7 R 6 5 4 AIEN ADCO 0 0 3 2 1 0 1 1 COCO ADCH W Reset: 0 1 1 1 = Unimplemented or Reserved Figure 9-3. Status and Control Register (ADCSC1) Table 9-3. ADCSC1 Register Field Descriptions Field Description 7 COCO Conversion Complete Flag — The COCO flag is a read-only bit which is set each time a conversion is completed when the compare function is disabled (ACFE = 0).
Chapter 9 Analog-to-Digital Converter (S08ADC10V1) Figure 9-4. Input Channel Select (continued) 9.3.
Chapter 9 Analog-to-Digital Converter (S08ADC10V1) Table 9-4. ADCSC2 Register Field Descriptions (continued) Field Description 5 ACFE Compare Function Enable — ACFE is used to enable the compare function. 0 Compare function disabled 1 Compare function enabled 4 ACFGT Compare Function Greater Than Enable — ACFGT is used to configure the compare function to trigger when the result of the conversion of the input being monitored is greater than or equal to the compare value.
Chapter 9 Analog-to-Digital Converter (S08ADC10V1) R 7 6 5 4 3 2 1 0 ADR7 ADR6 ADR5 ADR4 ADR3 ADR2 ADR1 ADR0 0 0 0 0 0 0 0 0 W Reset: = Unimplemented or Reserved Figure 9-7. Data Result Low Register (ADCRL) 9.3.5 Compare Value High Register (ADCCVH) This register holds the upper two bits of the 10-bit compare value. These bits are compared to the upper two bits of the result following a conversion in 10-bit mode when the compare function is enabled.
Chapter 9 Analog-to-Digital Converter (S08ADC10V1) 7 6 5 4 3 2 1 0 R ADLPC ADIV ADLSMP MODE ADICLK W Reset: 0 0 0 0 0 0 0 0 Figure 9-10. Configuration Register (ADCCFG) Table 9-5. ADCCFG Register Field Descriptions Field Description 7 ADLPC Low Power Configuration — ADLPC controls the speed and power configuration of the successive approximation converter. This is used to optimize power consumption when higher sample rates are not required.
Chapter 9 Analog-to-Digital Converter (S08ADC10V1) Table 9-8. Input Clock Select ADICLK 9.3.8 Selected Clock Source 00 Bus clock 01 Bus clock divided by 2 10 Alternate clock (ALTCLK) 11 Asynchronous clock (ADACK) Pin Control 1 Register (APCTL1) The pin control registers are used to disable the I/O port control of MCU pins used as analog inputs. APCTL1 is used to control the pins associated with channels 0–7 of the ADC module.
Chapter 9 Analog-to-Digital Converter (S08ADC10V1) Table 9-9. APCTL1 Register Field Descriptions (continued) Field Description 1 ADPC1 ADC Pin Control 1 — ADPC1 is used to control the pin associated with channel AD1. 0 AD1 pin I/O control enabled 1 AD1 pin I/O control disabled 0 ADPC0 ADC Pin Control 0 — ADPC0 is used to control the pin associated with channel AD0. 0 AD0 pin I/O control enabled 1 AD0 pin I/O control disabled 9.3.
Chapter 9 Analog-to-Digital Converter (S08ADC10V1) Table 9-10. APCTL2 Register Field Descriptions (continued) Field Description 1 ADPC9 ADC Pin Control 9 — ADPC9 is used to control the pin associated with channel AD9. 0 AD9 pin I/O control enabled 1 AD9 pin I/O control disabled 0 ADPC8 ADC Pin Control 8 — ADPC8 is used to control the pin associated with channel AD8. 0 AD8 pin I/O control enabled 1 AD8 pin I/O control disabled 9.3.
Chapter 9 Analog-to-Digital Converter (S08ADC10V1) Table 9-11. APCTL3 Register Field Descriptions (continued) Field Description 1 ADPC17 ADC Pin Control 17 — ADPC17 is used to control the pin associated with channel AD17. 0 AD17 pin I/O control enabled 1 AD17 pin I/O control disabled 0 ADPC16 ADC Pin Control 16 — ADPC16 is used to control the pin associated with channel AD16. 0 AD16 pin I/O control enabled 1 AD16 pin I/O control disabled 9.
Chapter 9 Analog-to-Digital Converter (S08ADC10V1) are too fast, then the clock must be divided to the appropriate frequency. This divider is specified by the ADIV bits and can be divide-by 1, 2, 4, or 8. 9.4.2 Input Select and Pin Control The pin control registers (APCTL3, APCTL2, and APCTL1) are used to disable the I/O port control of the pins used as analog inputs.
Chapter 9 Analog-to-Digital Converter (S08ADC10V1) 9.4.4.2 Completing Conversions A conversion is completed when the result of the conversion is transferred into the data result registers, ADCRH and ADCRL. This is indicated by the setting of COCO. An interrupt is generated if AIEN is high at the time that COCO is set.
Chapter 9 Analog-to-Digital Converter (S08ADC10V1) result of the conversion is transferred to ADCRH and ADCRL upon completion of the conversion algorithm. If the bus frequency is less than the fADCK frequency, precise sample time for continuous conversions cannot be guaranteed when short sample is enabled (ADLSMP=0). If the bus frequency is less than 1/11th of the fADCK frequency, precise sample time for continuous conversions cannot be guaranteed when long sample is enabled (ADLSMP=1).
Chapter 9 Analog-to-Digital Converter (S08ADC10V1) 9.4.5 Automatic Compare Function The compare function can be configured to check for either an upper limit or lower limit. After the input is sampled and converted, the result is added to the two’s complement of the compare value (ADCCVH and ADCCVL). When comparing to an upper limit (ACFGT = 1), if the result is greater-than or equal-to the compare value, COCO is set.
Chapter 9 Analog-to-Digital Converter (S08ADC10V1) 9.4.7.2 Stop3 Mode With ADACK Enabled If ADACK is selected as the conversion clock, the ADC continues operation during stop3 mode. For guaranteed ADC operation, the MCU’s voltage regulator must remain active during stop3 mode. Consult the module introduction for configuration information for this MCU. If a conversion is in progress when the MCU enters stop3 mode, it continues until completion.
Chapter 9 Analog-to-Digital Converter (S08ADC10V1) 2. Update status and control register 2 (ADCSC2) to select the conversion trigger (hardware or software) and compare function options, if enabled. 3. Update status and control register 1 (ADCSC1) to select whether conversions will be continuous or completed only once, and to enable or disable conversion complete interrupts. The input channel on which conversions will be performed is also selected here. 9.5.1.
Chapter 9 Analog-to-Digital Converter (S08ADC10V1) RESET INITIALIZE ADC ADCCFG = $98 ADCSC2 = $00 ADCSC1 = $41 CHECK COCO=1? NO YES READ ADCRH THEN ADCRL TO CLEAR COCO BIT CONTINUE Figure 9-14. Initialization Flowchart for Example 9.6 Application Information This section contains information for using the ADC module in applications. The ADC has been designed to be integrated into a microcontroller for use in embedded control applications requiring an A/D converter. 9.6.
Chapter 9 Analog-to-Digital Converter (S08ADC10V1) In cases where separate power supplies are used for analog and digital power, the ground connection between these supplies must be at the VSSAD pin. This should be the only ground connection between these supplies if possible. The VSSAD pin makes a good single point ground location. 9.6.1.2 Analog Reference Pins In addition to the analog supplies, the ADC module has connections for two reference voltage inputs.
Chapter 9 Analog-to-Digital Converter (S08ADC10V1) 9.6.2 Sources of Error Several sources of error exist for A/D conversions. These are discussed in the following sections. 9.6.2.1 Sampling Error For proper conversions, the input must be sampled long enough to achieve the proper accuracy. Given the maximum input resistance of approximately 7kΩ and input capacitance of approximately 5.5 pF, sampling to within 1/4LSB (at 10-bit resolution) can be achieved within the minimum sample window (3.
Chapter 9 Analog-to-Digital Converter (S08ADC10V1) • • Average the result by converting the analog input many times in succession and dividing the sum of the results. Four samples are required to eliminate the effect of a 1LSB, one-time error. Reduce the effect of synchronous noise by operating off the asynchronous clock (ADACK) and averaging. Noise that is synchronous to ADCK cannot be averaged out. 9.6.2.
Chapter 9 Analog-to-Digital Converter (S08ADC10V1) converter yields the lower code (and vice-versa). However, even very small amounts of system noise can cause the converter to be indeterminate (between two codes) for a range of input voltages around the transition voltage. This range is normally around 1/2LSB and will increase with noise. This error may be reduced by repeatedly sampling the input and averaging the result. Additionally the techniques discussed in Section 9.6.2.3 will reduce this error.
Chapter 9 Analog-to-Digital Converter (S08ADC10V1) MC9S08SH32 Series Data Sheet, Rev.
Chapter 10 Inter-Integrated Circuit (S08IICV2) 10.1 Introduction The inter-integrated circuit (IIC) provides a method of communication between a number of devices. The interface is designed to operate up to 100 kbps with maximum bus loading and timing. The device is capable of operating at higher baud rates, up to a maximum of clock/20, with reduced bus loading. The maximum communication length and the number of devices that can be connected are limited by a maximum bus capacitance of 400 pF.
Chapter 10 Inter-Integrated Circuit (S08IICV2) BKGD/MS HCS08 CORE DEBUG MODULE (DBG) PTA6/TPM2CH0 8-BIT MODULO TIMER MODULE (MTIM) IRQ SCL IRQ IIC MODULE (IIC) LVD SERIAL PERIPHERAL INTERFACE MODULE (SPI) USER FLASH (MC9S08SH32 = 32,768 BYTES) (MC9S08SH16 = 16,384 BYTES) SERIAL COMMUNICATIONS INTERFACE MODULE (SCI) 16-BIT TIMER/PWM MODULE (TPM1) REAL-TIME COUNTER (RTC) 40-MHz INTERNAL CLOCK SOURCE (ICS) PTA1/PIA1/TPM2CH0/ADP1/ACMP– PTA0/PIA0/TPM1CH0/ADP0/ACMP+ SS MISO MOSI SPSCK RxD TxD PTB7/
Chapter 10 Inter-Integrated Circuit (S08IICV2) 10.1.
Chapter 10 Inter-Integrated Circuit (S08IICV2) 10.1.4 Block Diagram Figure 10-2 is a block diagram of the IIC. Address Data Bus Interrupt ADDR_DECODE CTRL_REG DATA_MUX FREQ_REG ADDR_REG STATUS_REG DATA_REG Input Sync Start Stop Arbitration Control Clock Control In/Out Data Shift Register Address Compare SCL SDA Figure 10-2. IIC Functional Block Diagram 10.2 External Signal Description This section describes each user-accessible pin signal. 10.2.
Chapter 10 Inter-Integrated Circuit (S08IICV2) Refer to the direct-page register summary in the memory chapter of this document for the absolute address assignments for all IIC registers. This section refers to registers and control bits only by their names. A Freescale-provided equate or header file is used to translate these names into the appropriate absolute addresses. 10.3.
Chapter 10 Inter-Integrated Circuit (S08IICV2) Table 10-3. IICF Field Descriptions Field 7–6 MULT 5–0 ICR Description IIC Multiplier Factor. The MULT bits define the multiplier factor, mul. This factor, along with the SCL divider, generates the IIC baud rate. The multiplier factor mul as defined by the MULT bits is provided below. 00 mul = 01 01 mul = 02 10 mul = 04 11 Reserved IIC Clock Rate. The ICR bits are used to prescale the bus clock for bit rate selection.
Chapter 10 Inter-Integrated Circuit (S08IICV2) Table 10-5.
Chapter 10 Inter-Integrated Circuit (S08IICV2) 10.3.3 IIC Control Register (IICC1) 7 6 5 4 3 IICEN IICIE MST TX TXAK R W Reset 2 1 0 0 0 0 0 0 RSTA 0 0 0 0 0 0 = Unimplemented or Reserved Figure 10-5. IIC Control Register (IICC1) Table 10-6. IICC1 Field Descriptions Field Description 7 IICEN IIC Enable. The IICEN bit determines whether the IIC module is enabled. 0 IIC is not enabled 1 IIC is enabled 6 IICIE IIC Interrupt Enable.
Chapter 10 Inter-Integrated Circuit (S08IICV2) 10.3.4 IIC Status Register (IICS) 7 R 6 TCF 5 4 BUSY IAAS 3 2 0 SRW ARBL 1 0 RXAK IICIF W Reset 1 0 0 0 0 0 0 0 = Unimplemented or Reserved Figure 10-6. IIC Status Register (IICS) Table 10-7. IICS Field Descriptions Field Description 7 TCF Transfer Complete Flag. This bit is set on the completion of a byte transfer. This bit is only valid during or immediately following a transfer to the IIC module or from the IIC module.
Chapter 10 Inter-Integrated Circuit (S08IICV2) 10.3.5 IIC Data I/O Register (IICD) 7 6 5 4 3 2 1 0 0 0 0 0 R DATA W Reset 0 0 0 0 Figure 10-7. IIC Data I/O Register (IICD) Table 10-8. IICD Field Descriptions Field Description 7–0 DATA Data — In master transmit mode, when data is written to the IICD, a data transfer is initiated. The most significant bit is sent first. In master receive mode, reading this register initiates receiving of the next byte of data.
Chapter 10 Inter-Integrated Circuit (S08IICV2) Table 10-9. IICC2 Field Descriptions Field Description 7 GCAEN General Call Address Enable. The GCAEN bit enables or disables general call address. 0 General call address is disabled 1 General call address is enabled 6 ADEXT Address Extension. The ADEXT bit controls the number of bits used for the slave address. 0 7-bit address scheme 1 10-bit address scheme 2–0 AD[10:8] Slave Address.
Chapter 10 Inter-Integrated Circuit (S08IICV2) msb SCL 1 SDA lsb 2 3 4 5 6 7 msb 8 9 AD7 AD6 AD5 AD4 AD3 AD2 AD1 R/W Start Signal 1 SDA 3 4 5 6 7 Calling Address 3 4 5 6 7 8 D7 D6 D5 D4 D3 D2 D1 D0 9 1 XX Read/ Ack Write Bit 9 No Ack Bit msb 8 AD7 AD6 AD5 AD4 AD3 AD2 AD1 R/W Start Signal 2 Data Byte lsb 2 1 Read/ Ack Write Bit Calling Address msb SCL XXX lsb Stop Signal lsb 2 3 4 5 6 7 8 9 AD7 AD6 AD5 AD4 AD3 AD2 AD1 R/W Repeated Start Signal
Chapter 10 Inter-Integrated Circuit (S08IICV2) 10.4.1.3 Data Transfer Before successful slave addressing is achieved, the data transfer can proceed byte-by-byte in a direction specified by the R/W bit sent by the calling master. All transfers that come after an address cycle are referred to as data transfers, even if they carry sub-address information for the slave device Each data byte is 8 bits long.
Chapter 10 Inter-Integrated Circuit (S08IICV2) the transition from master to slave mode does not generate a stop condition. Meanwhile, a status bit is set by hardware to indicate loss of arbitration. 10.4.1.7 Clock Synchronization Because wire-AND logic is performed on the SCL line, a high-to-low transition on the SCL line affects all the devices connected on the bus.
Chapter 10 Inter-Integrated Circuit (S08IICV2) 10.4.2 10-bit Address For 10-bit addressing, 0x11110 is used for the first 5 bits of the first address byte. Various combinations of read/write formats are possible within a transfer that includes 10-bit addressing. 10.4.2.1 Master-Transmitter Addresses a Slave-Receiver The transfer direction is not changed (see Table 10-10).
Chapter 10 Inter-Integrated Circuit (S08IICV2) 10.4.3 General Call Address General calls can be requested in 7-bit address or 10-bit address. If the GCAEN bit is set, the IIC matches the general call address as well as its own slave address. When the IIC responds to a general call, it acts as a slave-receiver and the IAAS bit is set after the address cycle.
Chapter 10 Inter-Integrated Circuit (S08IICV2) Arbitration is lost in the following circumstances: • SDA sampled as a low when the master drives a high during an address or data transmit cycle. • SDA sampled as a low when the master drives a high during the acknowledge bit of a data receive cycle. • A start cycle is attempted when the bus is busy. • A repeated start cycle is requested in slave mode. • A stop condition is detected when the master did not request it.
Chapter 10 Inter-Integrated Circuit (S08IICV2) 10.7 1. 2. 3. 4. 5. 1. 2. 3. 4. 5. 6. 7.
Chapter 10 Inter-Integrated Circuit (S08IICV2) Clear IICIF Master Mode ? Y TX N Y RX Tx/Rx ? Arbitration Lost ? N Last Byte Transmitted ? N Clear ARBL Y RXAK=0 ? Last Byte to Be Read ? N N N Y Y IAAS=1 ? Y IAAS=1 ? Y Address Transfer See Note 1 Y End of Addr Cycle (Master Rx) ? Y Y (Read) 2nd Last Byte to Be Read ? N SRW=1 ? Write Next Byte to IICD Set TXACK =1 Generate Stop Signal (MST = 0) Switch to Rx Mode Generate Stop Signal (MST = 0) Read Data from IICD and Store A
Chapter 10 Inter-Integrated Circuit (S08IICV2) MC9S08SH32 Series Data Sheet, Rev.
Chapter 11 Internal Clock Source (S08ICSV2) 11.1 Introduction The internal clock source (ICS) module provides clock source choices for the MCU. The module contains a frequency-locked loop (FLL) as a clock source that is controllable by either an internal or an external reference clock. The module can provide this FLL clock or either of the internal or external reference clocks as a source for the MCU system clock.
Chapter 11 Internal Clock Source (S08ICSV2) BKGD/MS HCS08 CORE DEBUG MODULE (DBG) PTA6/TPM2CH0 IRQ SCL IRQ IIC MODULE (IIC) LVD SERIAL PERIPHERAL INTERFACE MODULE (SPI) USER FLASH (MC9S08SH32 = 32,768 BYTES) (MC9S08SH16 = 16,384 BYTES) SERIAL COMMUNICATIONS INTERFACE MODULE (SCI) 16-BIT TIMER/PWM MODULE (TPM1) REAL-TIME COUNTER (RTC) 40-MHz INTERNAL CLOCK SOURCE (ICS) PTA1/PIA1/TPM2CH0/ADP1/ACMP– PTA0/PIA0/TPM1CH0/ADP0/ACMP+ SS MISO MOSI SPSCK PTB7/SCL/EXTAL PTB6/SDA/XTAL RxD TxD 16-BIT TIME
Chapter 11 Internal Clock Source (S08ICSV2) 11.1.2 Features Key features of the ICS module follow. For device specific information, refer to the ICS Characteristics in the Electricals section of the documentation. • Frequency-locked loop (FLL) is trimmable for accuracy — 0.
Chapter 11 Internal Clock Source (S08ICSV2) Optional External Reference Clock Source Block RANGE HGO EREFS ERCLKEN EREFSTEN IRCLKEN IREFSTEN ICSERCLK ICSIRCLK CLKS BDIV / 2n Internal Reference Clock 9 IREFS ICSOUT n=0-3 LP DCO DCOOUT /2 ICSLCLK TRIM ICSFFCLK 9 / 2n RDIV_CLK Filter n=0-7 FLL RDIV Internal Clock Source Block Figure 11-2. Internal Clock Source (ICS) Block Diagram 11.1.
Chapter 11 Internal Clock Source (S08ICSV2) 11.1.4.4 FLL Bypassed Internal Low Power (FBILP) In FLL bypassed internal low power mode, the FLL is disabled and bypassed, and the ICS supplies a clock derived from the internal reference clock. The BDC clock is not available. 11.1.4.5 FLL Bypassed External (FBE) In FLL bypassed external mode, the FLL is enabled and controlled by an external reference clock, but is bypassed. The ICS supplies a clock derived from the external reference clock.
Chapter 11 Internal Clock Source (S08ICSV2) 11.3.1 ICS Control Register 1 (ICSC1) 7 6 5 4 3 2 1 0 IREFS IRCLKEN IREFSTEN 1 0 0 R CLKS RDIV W Reset: 0 0 0 0 0 Figure 11-3. ICS Control Register 1 (ICSC1) Table 11-2. ICS Control Register 1 Field Descriptions Field Description 7:6 CLKS Clock Source Select — Selects the clock source that controls the bus frequency. The actual bus frequency depends on the value of the BDIV bits. 00 Output of FLL is selected.
Chapter 11 Internal Clock Source (S08ICSV2) 11.3.2 ICS Control Register 2 (ICSC2) 7 6 5 4 3 2 RANGE HGO LP EREFS 0 0 0 0 1 0 R BDIV ERCLKEN EREFSTEN W Reset: 0 1 0 0 Figure 11-4. ICS Control Register 2 (ICSC2) Table 11-3. ICS Control Register 2 Field Descriptions Field Description 7:6 BDIV Bus Frequency Divider — Selects the amount to divide down the clock source selected by the CLKS bits. This controls the bus frequency.
Chapter 11 Internal Clock Source (S08ICSV2) 11.3.3 ICS Trim Register (ICSTRM) 7 6 5 4 3 2 1 0 R TRIM W POR: 1 0 0 0 0 0 0 0 Reset: U U U U U U U U Figure 11-5. ICS Trim Register (ICSTRM) Table 11-4. ICS Trim Register Field Descriptions Field Description 7:0 TRIM ICS Trim Setting — The TRIM bits control the internal reference clock frequency by controlling the internal reference clock period. The bits’ effect are binary weighted (i.e., bit 1 will adjust twice as much as bit 0).
Chapter 11 Internal Clock Source (S08ICSV2) Table 11-5. ICS Status and Control Register Field Descriptions (continued) Field Description 1 OSC Initialization — If the external reference clock is selected by ERCLKEN or by the ICS being in FEE, FBE, or FBELP mode, and if EREFS is set, then this bit is set after the initialization cycles of the external oscillator clock have completed. This bit is only cleared when either ERCLKEN or EREFS are cleared.
Chapter 11 Internal Clock Source (S08ICSV2) • • • CLKS bits are written to 00 IREFS bit is written to 1 RDIV bits are written to divide trimmed reference clock to be within the range of 31.25 kHz to 39.0625 kHz. In FLL engaged internal mode, the ICSOUT clock is derived from the FLL clock, which is controlled by the internal reference clock. The FLL loop will lock the frequency to 1024 times the reference frequency, as selected by the RDIV bits.
Chapter 11 Internal Clock Source (S08ICSV2) 11.4.1.5 FLL Bypassed External (FBE) The FLL bypassed external (FBE) mode is entered when all the following conditions occur: • CLKS bits are written to 10. • IREFS bit is written to 0. • BDM mode is active or LP bit is written to 0. In FLL bypassed external mode, the ICSOUT clock is derived from the external reference clock.
Chapter 11 Internal Clock Source (S08ICSV2) The CLKS bits can also be changed at anytime, but the RDIV bits must be changed simultaneously so that the resulting frequency stays in the range of 31.25 kHz to 39.0625 kHz. The actual switch to the newly selected clock will not occur until after a few full cycles of the new clock. If the newly selected clock is not available, the previous clock will remain selected. 11.4.
Chapter 11 Internal Clock Source (S08ICSV2) If EREFSTEN is set and the ERCLKEN bit is written to 1, the external reference clock will keep running during stop mode in order to provide a fast recovery upon exiting stop. 11.4.7 Fixed Frequency Clock The ICS presents the divided FLL reference clock as ICSFFCLK for use as an additional clock source for peripheral modules.
Chapter 11 Internal Clock Source (S08ICSV2) MC9S08SH32 Series Data Sheet, Rev.
Chapter 12 Modulo Timer (S08MTIMV1) 12.1 Introduction The MTIM is a simple 8-bit timer with several software selectable clock sources and a programmable interrupt. The central component of the MTIM is the 8-bit counter, which can operate as a free-running counter or a modulo counter. A timer overflow interrupt can be enabled to generate periodic interrupts for time-based software loops. Figure 12-1 shows the MC9S08SH32 Series block diagram with the MTIM highlighted. 12.1.
Chapter 12 Modulo Timer (S08MTIMV1) BKGD/MS HCS08 CORE DEBUG MODULE (DBG) PTA6/TPM2CH0 HCS08 SYSTEM CONTROL RESETS AND INTERRUPTS MODES OF OPERATION POWER MANAGEMENT IRQ SCL IRQ IIC MODULE (IIC) LVD SERIAL PERIPHERAL INTERFACE MODULE (SPI) USER FLASH (MC9S08SH32 = 32,768 BYTES) (MC9S08SH16 = 16,384 BYTES) SERIAL COMMUNICATIONS INTERFACE MODULE (SCI) PTA5/IRQ/TCLK/RESET 16-BIT TIMER/PWM MODULE (TPM1) REAL-TIME COUNTER (RTC) 40-MHz INTERNAL CLOCK SOURCE (ICS) PTA1/PIA1/TPM2CH0/ADP1/ACMP– PTA0/PIA
Chapter 12 Modulo Timer (S08MTIMV1) 12.1.
Chapter 12 Modulo Timer (S08MTIMV1) 12.1.4 Block Diagram The block diagram for the modulo timer module is shown Figure 12-2. BUSCLK XCLK TCLK SYNC MTIM INTERRUPT REQUEST CLOCK SOURCE SELECT PRESCALE AND SELECT DIVIDE BY CLKS PS 8-BIT COUNTER (MTIMCNT) TRST TSTP 8-BIT COMPARATOR TOF 8-BIT MODULO (MTIMMOD) TOIE Figure 12-2. Modulo Timer (MTIM) Block Diagram 12.
Chapter 12 Modulo Timer (S08MTIMV1) 12.3 Register Definition Figure 12-3 is a summary of MTIM registers. Name MTIMSC MTIMCLK MTIMCNT MTIMMOD 7 R TOF W R 0 W 6 TOIE 0 5 4 0 TRST TSTP CLKS R 3 2 1 0 0 0 0 0 PS COUNT W R MOD W Figure 12-3.
Chapter 12 Modulo Timer (S08MTIMV1) 12.3.1 MTIM Status and Control Register (MTIMSC) MTIMSC contains the overflow status flag and control bits which are used to configure the interrupt enable, reset the counter, and stop the counter. 7 R 6 5 TOF 0 TOIE W Reset: 4 3 2 1 0 0 0 0 0 0 0 0 0 TSTP TRST 0 0 0 1 Figure 12-4. MTIM Status and Control Register Table 12-2.
Chapter 12 Modulo Timer (S08MTIMV1) 12.3.2 MTIM Clock Configuration Register (MTIMCLK) MTIMCLK contains the clock select bits (CLKS) and the prescaler select bits (PS). R 7 6 0 0 5 4 3 2 CLKS 1 0 0 0 PS W Reset: 0 0 0 0 0 0 Figure 12-5. MTIM Clock Configuration Register Table 12-3. MTIM Clock Configuration Register Field Description Field 7:6 5:4 CLKS 3:0 PS Description Unused register bits, always read 0.
Chapter 12 Modulo Timer (S08MTIMV1) 12.3.3 MTIM Counter Register (MTIMCNT) MTIMCNT is the read-only value of the current MTIM count of the 8-bit counter. 7 6 5 4 R 3 2 1 0 0 0 0 0 COUNT W Reset: 0 0 0 0 Figure 12-6. MTIM Counter Register Table 12-4. MTIM Counter Register Field Description Field Description 7:0 COUNT MTIM Count — These eight read-only bits contain the current value of the 8-bit counter. Writes have no effect to this register. Reset clears the count to $00. 12.3.
Chapter 12 Modulo Timer (S08MTIMV1) 12.4 Functional Description The MTIM is composed of a main 8-bit up-counter with an 8-bit modulo register, a clock source selector, and a prescaler block with nine selectable values. The module also contains software selectable interrupt logic. The MTIM counter (MTIMCNT) has three modes of operation: stopped, free-running, and modulo. Out of reset, the counter is stopped.
Chapter 12 Modulo Timer (S08MTIMV1) 12.4.1 MTIM Operation Example This section shows an example of the MTIM operation as the counter reaches a matching value from the modulo register. selected clock source MTIM clock (PS=%0010) MTIMCNT $A7 $A8 $A9 $AA $00 $01 TOF MTIMMOD: $AA Figure 12-8. MTIM counter overflow example In the example of Figure 12-8, the selected clock source could be any of the five possible choices. The prescaler is set to PS = %0010 or divide-by-4.
Chapter 13 Real-Time Counter (S08RTCV1) 13.1 Introduction The RTC module consists of one 8-bit counter, one 8-bit comparator, several binary-based and decimal-based prescaler dividers, two clock sources, and one programmable periodic interrupt. This module can be used for time-of-day, calendar or any task scheduling functions. It can also serve as a cyclic wake up from low power modes without the need of external components. MC9S08SH32 Series Data Sheet, Rev.
Chapter 13 Real-Time Counter (S08RTCV1) BKGD/MS HCS08 CORE DEBUG MODULE (DBG) PTA6/TPM2CH0 HCS08 SYSTEM CONTROL RESETS AND INTERRUPTS MODES OF OPERATION POWER MANAGEMENT IRQ SCL IRQ IIC MODULE (IIC) LVD SERIAL PERIPHERAL INTERFACE MODULE (SPI) USER FLASH (MC9S08SH32 = 32,768 BYTES) (MC9S08SH16 = 16,384 BYTES) SERIAL COMMUNICATIONS INTERFACE MODULE (SCI) PTA5/IRQ/TCLK/RESET 16-BIT TIMER/PWM MODULE (TPM1) REAL-TIME COUNTER (RTC) 40-MHz INTERNAL CLOCK SOURCE (ICS) PTA1/PIA1/TPM2CH0/ADP1/ACMP– PTA0
Chapter 13 Real-Time Counter (S08RTCV1) 13.1.1 Features Features of the RTC module include: • 8-bit up-counter — 8-bit modulo match limit — Software controllable periodic interrupt on match • Three software selectable clock sources for input to prescaler with selectable binary-based and decimal-based divider values — 1-kHz internal low-power oscillator (LPO) — External clock (ERCLK) — 32-kHz internal clock (IRCLK) 13.1.
Chapter 13 Real-Time Counter (S08RTCV1) 13.1.3 Block Diagram The block diagram for the RTC module is shown in Figure 13-2. LPO Clock Source Select ERCLK IRCLK 8-Bit Modulo (RTCMOD) RTCLKS VDD RTCLKS[0] RTCPS Prescaler Divide-By Q D Background Mode E 8-Bit Comparator RTC Clock RTC Interrupt Request RTIF R Write 1 to RTIF 8-Bit Counter (RTCCNT) RTIE Figure 13-2. Real-Time Counter (RTC) Block Diagram 13.2 External Signal Description The RTC does not include any off-chip signals. 13.
Chapter 13 Real-Time Counter (S08RTCV1) 13.3.1 RTC Status and Control Register (RTCSC) RTCSC contains the real-time interrupt status flag (RTIF), the clock select bits (RTCLKS), the real-time interrupt enable bit (RTIE), and the prescaler select bits (RTCPS). 7 6 5 4 3 2 1 0 0 0 R RTIF RTCLKS RTIE RTCPS W Reset: 0 0 0 0 0 0 Figure 13-3. RTC Status and Control Register (RTCSC) Table 13-2.
Chapter 13 Real-Time Counter (S08RTCV1) 13.3.2 RTC Counter Register (RTCCNT) RTCCNT is the read-only value of the current RTC count of the 8-bit counter. 7 6 5 4 R 3 2 1 0 0 0 0 0 RTCCNT W Reset: 0 0 0 0 Figure 13-4. RTC Counter Register (RTCCNT) Table 13-4. RTCCNT Field Descriptions Field Description 7:0 RTCCNT RTC Count. These eight read-only bits contain the current value of the 8-bit counter. Writes have no effect to this register.
Chapter 13 Real-Time Counter (S08RTCV1) RTCPS and the RTCLKS[0] bit select the desired divide-by value. If a different value is written to RTCPS, the prescaler and RTCCNT counters are reset to 0x00. Table 13-6 shows different prescaler period values. Table 13-6. Prescaler Period RTCPS 1-kHz Internal Clock (RTCLKS = 00) 1-MHz External Clock 32-kHz Internal Clock 32-kHz Internal Clock (RTCLKS = 01) (RTCLKS = 10) (RTCLKS = 11) 0000 Off Off Off Off 0001 8 ms 1.024 ms 250 μs 32 ms 0010 32 ms 2.
Chapter 13 Real-Time Counter (S08RTCV1) Internal 1-kHz Clock Source RTC Clock (RTCPS = 0xA) RTCCNT 0x52 0x53 0x54 0x55 0x00 0x01 RTIF RTCMOD 0x55 Figure 13-6. RTC Counter Overflow Example In the example of Figure 13-6, the selected clock source is the 1-kHz internal oscillator clock source. The prescaler (RTCPS) is set to 0xA or divide-by-4. The modulo value in the RTCMOD register is set to 0x55.
Chapter 13 Real-Time Counter (S08RTCV1) #pragma TRAP_PROC void RTC_ISR(void) { /* Clear the interrupt flag */ RTCSC.byte = RTCSC.byte | 0x80; /* RTC interrupts every 1 Second */ Seconds++; /* 60 seconds in a minute */ if (Seconds > 59){ Minutes++; Seconds = 0; } /* 60 minutes in an hour */ if (Minutes > 59){ Hours++; Minutes = 0; } /* 24 hours in a day */ if (Hours > 23){ Days ++; Hours = 0; } } MC9S08SH32 Series Data Sheet, Rev.
Chapter 13 Real-Time Counter (S08RTCV1) MC9S08SH32 Series Data Sheet, Rev.
Chapter 14 Serial Communications Interface (S08SCIV4) 14.1 Introduction Figure 14-1 shows the MC9S08SH32 Series block diagram with the SCI module highlighted. MC9S08SH32 Series Data Sheet, Rev.
Chapter 14 Serial Communications Interface (S08SCIV4) BKGD/MS HCS08 CORE DEBUG MODULE (DBG) PTA6/TPM2CH0 IRQ SCL IRQ IIC MODULE (IIC) LVD SERIAL PERIPHERAL INTERFACE MODULE (SPI) USER FLASH (MC9S08SH32 = 32,768 BYTES) (MC9S08SH16 = 16,384 BYTES) SERIAL COMMUNICATIONS INTERFACE MODULE (SCI) 16-BIT TIMER/PWM MODULE (TPM1) REAL-TIME COUNTER (RTC) 40-MHz INTERNAL CLOCK SOURCE (ICS) PTA1/PIA1/TPM2CH0/ADP1/ACMP– PTA0/PIA0/TPM1CH0/ADP0/ACMP+ SS MISO MOSI SPSCK PTB7/SCL/EXTAL PTB6/SDA/XTAL RxD TxD 1
Chapter 14 Serial Communications Interface (S08SCIV4) 14.1.
Chapter 14 Serial Communications Interface (S08SCIV4) 14.1.3 Block Diagram Figure 14-2 shows the transmitter portion of the SCI.
Chapter 14 Serial Communications Interface (S08SCIV4) Figure 14-3 shows the receiver portion of the SCI.
Chapter 14 Serial Communications Interface (S08SCIV4) 14.2 Register Definition The SCI has eight 8-bit registers to control baud rate, select SCI options, report SCI status, and for transmit/receive data. Refer to the direct-page register summary in the Memory chapter of this data sheet for the absolute address assignments for all SCI registers. This section refers to registers and control bits only by their names.
Chapter 14 Serial Communications Interface (S08SCIV4) 7 6 5 4 3 2 1 0 SBR7 SBR6 SBR5 SBR4 SBR3 SBR2 SBR1 SBR0 0 0 0 0 0 1 0 0 R W Reset Figure 14-5. SCI Baud Rate Register (SCIxBDL) Table 14-2. SCIxBDL Field Descriptions Field 7:0 SBR[7:0] 14.2.2 Description Baud Rate Modulo Divisor — These 13 bits in SBR[12:0] are referred to collectively as BR, and they set the modulo divide rate for the SCI baud rate generator.
Chapter 14 Serial Communications Interface (S08SCIV4) Table 14-3. SCIxC1 Field Descriptions (continued) Field 3 WAKE Description Receiver Wakeup Method Select — Refer to Section 14.3.3.2, “Receiver Wakeup Operation” for more information. 0 Idle-line wakeup. 1 Address-mark wakeup. 2 ILT Idle Line Type Select — Setting this bit to 1 ensures that the stop bit and logic 1 bits at the end of a character do not count toward the 10 or 11 bit times of logic high level needed by the idle line detection logic.
Chapter 14 Serial Communications Interface (S08SCIV4) Table 14-4. SCIxC2 Field Descriptions (continued) Field Description 3 TE Transmitter Enable 0 Transmitter off. 1 Transmitter on. TE must be 1 in order to use the SCI transmitter. When TE = 1, the SCI forces the TxD pin to act as an output for the SCI system. When the SCI is configured for single-wire operation (LOOPS = RSRC = 1), TXDIR controls the direction of traffic on the single SCI communication line (TxD pin).
Chapter 14 Serial Communications Interface (S08SCIV4) Table 14-5. SCIxS1 Field Descriptions Field Description 7 TDRE Transmit Data Register Empty Flag — TDRE is set out of reset and when a transmit data value transfers from the transmit data buffer to the transmit shifter, leaving room for a new character in the buffer. To clear TDRE, read SCIxS1 with TDRE = 1 and then write to the SCI data register (SCIxD). 0 Transmit data register (buffer) full. 1 Transmit data register (buffer) empty.
Chapter 14 Serial Communications Interface (S08SCIV4) Table 14-5. SCIxS1 Field Descriptions (continued) Field Description 1 FE Framing Error Flag — FE is set at the same time as RDRF when the receiver detects a logic 0 where the stop bit was expected. This suggests the receiver was not properly aligned to a character frame. To clear FE, read SCIxS1 with FE = 1 and then read the SCI data register (SCIxD). 0 No framing error detected. This does not guarantee the framing is correct. 1 Framing error.
Chapter 14 Serial Communications Interface (S08SCIV4) Table 14-6. SCIxS2 Field Descriptions (continued) Field 1 LBKDE 0 RAF 1 Description LIN Break Detection Enable— LBKDE is used to select a longer break character detection length. While LBKDE is set, framing error (FE) and receive data register full (RDRF) flags are prevented from setting. 0 Break character is detected at length of 10 bit times (11 if M = 1). 1 Break character is detected at length of 11 bit times (12 if M = 1).
Chapter 14 Serial Communications Interface (S08SCIV4) Table 14-7. SCIxC3 Field Descriptions (continued) Field 4 TXINV1 1 Description Transmit Data Inversion — Setting this bit reverses the polarity of the transmitted data output. 0 Transmit data not inverted 1 Transmit data inverted 3 ORIE Overrun Interrupt Enable — This bit enables the overrun flag (OR) to generate hardware interrupt requests. 0 OR interrupts disabled (use polling). 1 Hardware interrupt requested when OR = 1.
Chapter 14 Serial Communications Interface (S08SCIV4) MODULO DIVIDE BY (1 THROUGH 8191) BUSCLK SBR12:SBR0 BAUD RATE GENERATOR OFF IF [SBR12:SBR0] = 0 DIVIDE BY 16 Tx BAUD RATE Rx SAMPLING CLOCK (16 × BAUD RATE) BAUD RATE = BUSCLK [SBR12:SBR0] × 16 Figure 14-12. SCI Baud Rate Generation SCI communications require the transmitter and receiver (which typically derive baud rates from independent clock sources) to use the same baud rate.
Chapter 14 Serial Communications Interface (S08SCIV4) Writing 0 to TE does not immediately release the pin to be a general-purpose I/O pin. Any transmit activity that is in progress must first be completed. This includes data characters in progress, queued idle characters, and queued break characters. 14.3.2.1 Send Break and Queued Idle The SBK control bit in SCIxC2 is used to send break characters which were originally used to gain the attention of old teletype receivers.
Chapter 14 Serial Communications Interface (S08SCIV4) flag is set. If RDRF was already set indicating the receive data register (buffer) was already full, the overrun (OR) status flag is set and the new data is lost. Because the SCI receiver is double-buffered, the program has one full character time after RDRF is set before the data in the receive data buffer must be read to avoid a receiver overrun.
Chapter 14 Serial Communications Interface (S08SCIV4) message characters. At the end of a message, or at the beginning of the next message, all receivers automatically force RWU to 0 so all receivers wake up in time to look at the first character(s) of the next message. 14.3.3.2.1 Idle-Line Wakeup When WAKE = 0, the receiver is configured for idle-line wakeup. In this mode, RWU is cleared automatically when the receiver detects a full character time of the idle-line level.
Chapter 14 Serial Communications Interface (S08SCIV4) Instead of hardware interrupts, software polling may be used to monitor the TDRE and TC status flags if the corresponding TIE or TCIE local interrupt masks are 0s. When a program detects that the receive data register is full (RDRF = 1), it gets the data from the receive data register by reading SCIxD. The RDRF flag is cleared by reading SCIxS1 while RDRF = 1 and then reading SCIxD.
Chapter 14 Serial Communications Interface (S08SCIV4) 14.3.5.2 Stop Mode Operation During all stop modes, clocks to the SCI module are halted. In stop1 and stop2 modes, all SCI register data is lost and must be re-initialized upon recovery from these two stop modes. No SCI module registers are affected in stop3 mode. The receive input active edge detect circuit is still active in stop3 mode, but not in stop2. .
Chapter 14 Serial Communications Interface (S08SCIV4) MC9S08SH32 Series Data Sheet, Rev.
Chapter 15 Serial Peripheral Interface (S08SPIV3) 15.1 Introduction The serial peripheral interface (SPI) module provides for full-duplex, synchronous, serial communication between the MCU and peripheral devices. These peripheral devices can include other microcontrollers, analog-to-digital converters, shift registers, sensors, memories, and so forth. The SPI runs at a baud rate up to that of the bus clock divided by two in master mode and bus clock divided by four in slave mode.
Chapter 15 Serial Peripheral Interface (S08SPIV3) BKGD/MS HCS08 CORE DEBUG MODULE (DBG) PTA6/TPM2CH0 HCS08 SYSTEM CONTROL RESETS AND INTERRUPTS MODES OF OPERATION POWER MANAGEMENT IRQ SCL IRQ IIC MODULE (IIC) LVD SERIAL PERIPHERAL INTERFACE MODULE (SPI) USER FLASH (MC9S08SH32 = 32,768 BYTES) (MC9S08SH16 = 16,384 BYTES) SERIAL COMMUNICATIONS INTERFACE MODULE (SCI) PTA5/IRQ/TCLK/RESET 16-BIT TIMER/PWM MODULE (TPM1) REAL-TIME COUNTER (RTC) 40-MHz INTERNAL CLOCK SOURCE (ICS) PTA1/PIA1/TPM2CH0/ADP1/
Chapter 15 Serial Peripheral Interface (S08SPIV3) 15.1.1 Features Features of the SPI module include: • Master or slave mode operation • Full-duplex or single-wire bidirectional option • Programmable transmit bit rate • Double-buffered transmit and receive • Serial clock phase and polarity options • Slave select output • Selectable MSB-first or LSB-first shifting 15.1.
Chapter 15 Serial Peripheral Interface (S08SPIV3) The most common uses of the SPI system include connecting simple shift registers for adding input or output ports or connecting small peripheral devices such as serial A/D or D/A converters. Although Figure 15-2 shows a system where data is exchanged between two MCUs, many practical systems involve simpler connections where data is unidirectionally transferred from the master MCU to a slave or from a slave to the master MCU. 15.1.2.
Chapter 15 Serial Peripheral Interface (S08SPIV3) PIN CONTROL M SPE MOSI (MOMI) S Tx BUFFER (WRITE SPIxD) ENABLE SPI SYSTEM M SHIFT OUT SPI SHIFT REGISTER SHIFT IN MISO (SISO) S SPC0 Rx BUFFER (READ SPIxD) BIDIROE SHIFT DIRECTION LSBFE SHIFT CLOCK Rx BUFFER FULL Tx BUFFER EMPTY MASTER CLOCK BUS RATE CLOCK SPIBR CLOCK GENERATOR MSTR CLOCK LOGIC SLAVE CLOCK MASTER/SLAVE M SPSCK S MASTER/ SLAVE MODE SELECT MODFEN SSOE MODE FAULT DETECTION SS SPRF SPTEF SPTIE MODF SPIE SPI INTERRUPT
Chapter 15 Serial Peripheral Interface (S08SPIV3) BUS CLOCK PRESCALER CLOCK RATE DIVIDER DIVIDE BY 1, 2, 3, 4, 5, 6, 7, or 8 DIVIDE BY 2, 4, 8, 16, 32, 64, 128, or 256 SPPR2:SPPR1:SPPR0 SPR2:SPR1:SPR0 MASTER SPI BIT RATE Figure 15-4. SPI Baud Rate Generation 15.2 External Signal Description The SPI optionally shares four port pins. The function of these pins depends on the settings of SPI control bits.
Chapter 15 Serial Peripheral Interface (S08SPIV3) 15.3 Modes of Operation 15.3.1 SPI in Stop Modes The SPI is disabled in all stop modes, regardless of the settings before executing the STOP instruction. During either stop1 or stop2 mode, the SPI module will be fully powered down. Upon wake-up from stop1 or stop2 mode, the SPI module will be in the reset state. During stop3 mode, clocks to the SPI module are halted. No registers are affected.
Chapter 15 Serial Peripheral Interface (S08SPIV3) Table 15-1. SPIxC1 Field Descriptions (continued) Field Description 4 MSTR Master/Slave Mode Select 0 SPI module configured as a slave SPI device 1 SPI module configured as a master SPI device 3 CPOL Clock Polarity — This bit effectively places an inverter in series with the clock signal from a master SPI or to a slave SPI device. Refer to Section 15.5.1, “SPI Clock Formats” for more details.
Chapter 15 Serial Peripheral Interface (S08SPIV3) Table 15-3. SPIxC2 Register Field Descriptions Field Description 4 MODFEN Master Mode-Fault Function Enable — When the SPI is configured for slave mode, this bit has no meaning or effect. (The SS pin is the slave select input.) In master mode, this bit determines how the SS pin is used (refer to Table 15-2 for more details).
Chapter 15 Serial Peripheral Interface (S08SPIV3) Table 15-5. SPI Baud Rate Prescaler Divisor SPPR2:SPPR1:SPPR0 Prescaler Divisor 0:0:0 1 0:0:1 2 0:1:0 3 0:1:1 4 1:0:0 5 1:0:1 6 1:1:0 7 1:1:1 8 Table 15-6. SPI Baud Rate Divisor 15.4.4 SPR2:SPR1:SPR0 Rate Divisor 0:0:0 2 0:0:1 4 0:1:0 8 0:1:1 16 1:0:0 32 1:0:1 64 1:1:0 128 1:1:1 256 SPI Status Register (SPIxS) This register has three read-only status bits. Bits 6, 3, 2, 1, and 0 are not implemented and always read 0.
Chapter 15 Serial Peripheral Interface (S08SPIV3) Table 15-7. SPIxS Register Field Descriptions Field Description 7 SPRF SPI Read Buffer Full Flag — SPRF is set at the completion of an SPI transfer to indicate that received data may be read from the SPI data register (SPIxD). SPRF is cleared by reading SPRF while it is set, then reading the SPI data register.
Chapter 15 Serial Peripheral Interface (S08SPIV3) 15.5 Functional Description An SPI transfer is initiated by checking for the SPI transmit buffer empty flag (SPTEF = 1) and then writing a byte of data to the SPI data register (SPIxD) in the master SPI device.
Chapter 15 Serial Peripheral Interface (S08SPIV3) pin from a master and the MISO waveform applies to the MISO output from a slave. The SS OUT waveform applies to the slave select output from a master (provided MODFEN and SSOE = 1). The master SS output goes to active low one-half SPSCK cycle before the start of the transfer and goes back high at the end of the eighth bit time of the transfer. The SS IN waveform applies to the slave select input of a slave. BIT TIME # (REFERENCE) 1 2 ...
Chapter 15 Serial Peripheral Interface (S08SPIV3) in LSBFE. Both variations of SPSCK polarity are shown, but only one of these waveforms applies for a specific transfer, depending on the value in CPOL. The SAMPLE IN waveform applies to the MOSI input of a slave or the MISO input of a master. The MOSI waveform applies to the MOSI output pin from a master and the MISO waveform applies to the MISO output from a slave.
Chapter 15 Serial Peripheral Interface (S08SPIV3) 15.5.2 SPI Interrupts There are three flag bits, two interrupt mask bits, and one interrupt vector associated with the SPI system. The SPI interrupt enable mask (SPIE) enables interrupts from the SPI receiver full flag (SPRF) and mode fault flag (MODF). The SPI transmit interrupt enable mask (SPTIE) enables interrupts from the SPI transmit buffer empty flag (SPTEF).
Chapter 15 Serial Peripheral Interface (S08SPIV3) MC9S08SH32 Series Data Sheet, Rev.
Chapter 16 Timer Pulse-Width Modulator (S08TPMV3) 16.1 Introduction The TPM uses one input/output (I/O) pin per channel, TPMxCHn where x is the TPM number (for example, 1 or 2) and n is the channel number (for example, 0–1). The TPM shares its I/O pins with general-purpose I/O port pins (refer to the Pins and Connections chapter for more information). All MC9S08SH32 Series MCUs have two TPM modules. Figure 16-1 shows the MC9S08SH32 Series block diagram with the TPM modules highlighted. 16.1.
Chapter 16 Timer Pulse-Width Modulator (S08TPMV3) BKGD/MS HCS08 CORE DEBUG MODULE (DBG) PTA6/TPM2CH0 HCS08 SYSTEM CONTROL RESETS AND INTERRUPTS MODES OF OPERATION POWER MANAGEMENT IRQ SCL IRQ IIC MODULE (IIC) LVD SERIAL PERIPHERAL INTERFACE MODULE (SPI) USER FLASH (MC9S08SH32 = 32,768 BYTES) (MC9S08SH16 = 16,384 BYTES) SERIAL COMMUNICATIONS INTERFACE MODULE (SCI) PTA5/IRQ/TCLK/RESET 16-BIT TIMER/PWM MODULE (TPM1) REAL-TIME COUNTER (RTC) 40-MHz INTERNAL CLOCK SOURCE (ICS) PTA1/PIA1/TPM2CH0/ADP1/
Chapter 16 Timer/PWM Module (S08TPMV3) 16.1.
Chapter 16 Timer/PWM Module (S08TPMV3) • • Edge-aligned PWM mode The value of a 16-bit modulo register plus 1 sets the period of the PWM output signal. The channel value register sets the duty cycle of the PWM output signal. The user may also choose the polarity of the PWM output signal. Interrupts are available at the end of the period and at the duty-cycle transition point.
Chapter 16 Timer/PWM Module (S08TPMV3) BUS CLOCK FIXED SYSTEM CLOCK SYNC EXTERNAL CLOCK CLOCK SOURCE SELECT OFF, BUS, FIXED SYSTEM CLOCK, EXT PRESCALE AND SELECT 1, 2, 4, 8, 16, 32, 64, or 128 CLKSB:CLKSA PS2:PS1:PS0 CPWMS 16-BIT COUNTER TOF COUNTER RESET TOIE INTERRUPT LOGIC 16-BIT COMPARATOR TPMxMODH:TPMxMODL CHANNEL 0 ELS0B ELS0A PORT LOGIC TPMxCH0 16-BIT COMPARATOR TPMxC0VH:TPMxC0VL CH0F INTERNAL BUS 16-BIT LATCH CHANNEL 1 MS0B MS0A ELS1B ELS1A CH0IE INTERRUPT LOGIC PORT LO
Chapter 16 Timer/PWM Module (S08TPMV3) The TPM channels are programmable independently as input capture, output compare, or edge-aligned PWM channels. Alternately, the TPM can be configured to produce CPWM outputs on all channels. When the TPM is configured for CPWMs, the counter operates as an up/down counter; input capture, output compare, and EPWM functions are not practical. If a channel is configured as input capture, an internal pullup device may be enabled for that channel.
Chapter 16 Timer/PWM Module (S08TPMV3) 16.2.1.1 EXTCLK — External Clock Source Control bits in the timer status and control register allow the user to select nothing (timer disable), the bus-rate clock (the normal default source), a crystal-related clock, or an external clock as the clock which drives the TPM prescaler and subsequently the 16-bit TPM counter. The external clock source is synchronized in the TPM.
Chapter 16 Timer/PWM Module (S08TPMV3) When a channel is configured for edge-aligned PWM (CPWMS=0, MSnB=1 and ELSnB:ELSnA not = 0:0), the data direction is overridden, the TPMxCHn pin is forced to be an output controlled by the TPM, and ELSnA controls the polarity of the PWM output signal on the pin. When ELSnB:ELSnA=1:0, the TPMxCHn pin is forced high at the start of each new period (TPMxCNT=0x0000), and the pin is forced low when the channel value register matches the timer counter.
Chapter 16 Timer/PWM Module (S08TPMV3) When the TPM is configured for center-aligned PWM (and ELSnB:ELSnA not = 0:0), the data direction for all channels in this TPM are overridden, the TPMxCHn pins are forced to be outputs controlled by the TPM, and the ELSnA bits control the polarity of each TPMxCHn output.
Chapter 16 Timer/PWM Module (S08TPMV3) 16.3 Register Definition This section consists of register descriptions in address order. A typical MCU system may contain multiple TPMs, and each TPM may have one to eight channels, so register names include placeholder characters to identify which TPM and which channel is being referenced. For example, TPMxCnSC refers to timer (TPM) x, channel n. TPM1C2SC would be the status and control register for channel 2 of timer 1. 16.3.
Chapter 16 Timer/PWM Module (S08TPMV3) Table 16-3. TPMxSC Field Descriptions (continued) Field Description 4–3 Clock source selects. As shown in Table 16-4, this 2-bit field is used to disable the TPM system or select one of CLKS[B:A] three clock sources to drive the counter prescaler. The fixed system clock source is only meaningful in systems with a PLL-based or FLL-based system clock. When there is no PLL or FLL, the fixed-system clock source is the same as the bus rate clock.
Chapter 16 Timer/PWM Module (S08TPMV3) Reset clears the TPM counter registers. Writing any value to TPMxCNTH or TPMxCNTL also clears the TPM counter (TPMxCNTH:TPMxCNTL) and resets the coherency mechanism, regardless of the data involved in the write. R 7 6 5 4 3 2 1 0 Bit 15 14 13 12 11 10 9 Bit 8 0 0 W Reset Any write to TPMxCNTH clears the 16-bit counter 0 0 0 0 0 0 Figure 16-8.
Chapter 16 Timer/PWM Module (S08TPMV3) When BDM is active, the coherency mechanism is frozen (unless reset by writing to TPMxSC register) such that the buffer latches remain in the state they were in when the BDM became active, even if one or both halves of the modulo register are written while BDM is active. Any write to the modulo registers bypasses the buffer latches and directly writes to the modulo register while BDM is active.
Chapter 16 Timer/PWM Module (S08TPMV3) Table 16-6. TPMxCnSC Field Descriptions Field Description 7 CHnF Channel n flag. When channel n is an input-capture channel, this read/write bit is set when an active edge occurs on the channel n pin. When channel n is an output compare or edge-aligned/center-aligned PWM channel, CHnF is set when the value in the TPM counter registers matches the value in the TPM channel n value registers.
Chapter 16 Timer/PWM Module (S08TPMV3) Table 16-7. Mode, Edge, and Level Selection CPWMS MSnB:MSnA ELSnB:ELSnA Mode Configuration 0 00 01 Input capture Capture on rising edge only 01 10 Capture on falling edge only 11 Capture on rising or falling edge 01 1X Output compare 10 Clear output on compare 11 Set output on compare 10 Edge-aligned PWM X1 1 XX High-true pulses (clear output on compare) Low-true pulses (set output on compare) 10 Center-aligned PWM X1 16.3.
Chapter 16 Timer/PWM Module (S08TPMV3) (becomes unlatched) when the TPMxCnSC register is written (whether BDM mode is active or not). Any write to the channel registers will be ignored during the input capture mode. When BDM is active, the coherency mechanism is frozen (unless reset by writing to TPMxCnSC register) such that the buffer latches remain in the state they were in when the BDM became active, even if one or both halves of the channel register are read while BDM is active.
Chapter 16 Timer/PWM Module (S08TPMV3) The following sections describe the main counter and each of the timer operating modes (input capture, output compare, edge-aligned PWM, and center-aligned PWM). Because details of pin operation and interrupt activity depend upon the operating mode, these topics will be covered in the associated mode explanation sections. 16.4.1 Counter All timer functions are based on the main 16-bit counter (TPMxCNTH:TPMxCNTL).
Chapter 16 Timer/PWM Module (S08TPMV3) Table 16-8. TPM Clock Source Selection CLKSB:CLKSA TPM Clock Source to Prescaler Input 00 No clock selected (TPM counter disabled) 01 Bus rate clock 10 Fixed system clock 11 External source The bus rate clock is the main system bus clock for the MCU. This clock source requires no synchronization because it is the clock that is used for all internal MCU activities including operation of the CPU and buses.
Chapter 16 Timer/PWM Module (S08TPMV3) 16.4.1.3 Counting Modes The main timer counter has two counting modes. When center-aligned PWM is selected (CPWMS=1), the counter operates in up/down counting mode. Otherwise, the counter operates as a simple up counter. As an up counter, the timer counter counts from 0x0000 through its terminal count and then continues with 0x0000. The terminal count is 0xFFFF or a modulus value in TPMxMODH:TPMxMODL.
Chapter 16 Timer/PWM Module (S08TPMV3) In output compare mode, values are transferred to the corresponding timer channel registers only after both 8-bit halves of a 16-bit register have been written and according to the value of CLKSB:CLKSA bits, so: • If (CLKSB:CLKSA = 0:0), the registers are updated when the second byte is written • If (CLKSB:CLKSA not = 0:0), the registers are updated at the next change of the TPM counter (end of the prescaler counting) after the second byte is written.
Chapter 16 Timer/PWM Module (S08TPMV3) the TPM counter is a free-running counter then the update is made when the TPM counter changes from 0xFFFE to 0xFFFF. 16.4.2.4 Center-Aligned PWM Mode This type of PWM output uses the up/down counting mode of the timer counter (CPWMS=1). The output compare value in TPMxCnVH:TPMxCnVL determines the pulse width (duty cycle) of the PWM signal while the period is determined by the value in TPMxMODH:TPMxMODL.
Chapter 16 Timer/PWM Module (S08TPMV3) Input capture, output compare, and edge-aligned PWM functions do not make sense when the counter is operating in up/down counting mode so this implies that all active channels within a TPM must be used in CPWM mode when CPWMS=1. The TPM may be used in an 8-bit MCU. The settings in the timer channel registers are buffered to ensure coherent 16-bit updates and to avoid unexpected PWM pulse widths.
Chapter 16 Timer/PWM Module (S08TPMV3) All TPM interrupts are listed in Table 16-9 which shows the interrupt name, the name of any local enable that can block the interrupt request from leaving the TPM and getting recognized by the separate interrupt processing logic. Table 16-9.
Chapter 16 Timer/PWM Module (S08TPMV3) 16.6.2.1.2 Center-Aligned PWM Case When CPWMS=1, TOF gets set when the timer counter changes direction from up-counting to down-counting at the end of the terminal count (the value in the modulo register). In this case the TOF corresponds to the end of a PWM period. 16.6.2.2 Channel Event Interrupt Description The meaning of channel interrupts depends on the channel’s current mode (input-capture, output-compare, edge-aligned PWM, or center-aligned PWM). 16.6.2.2.
Chapter 16 Timer/PWM Module (S08TPMV3) BDM mode returns the latched value of TPMxCNTH:L from the read buffer instead of the frozen TPM counter value. — This read coherency mechanism is cleared in TPM v3 in BDM mode if there is a write to TPMxSC, TPMxCNTH or TPMxCNTL. Instead, in these conditions the TPM v2 does not clear this read coherency mechanism. 3. Read of TPMxCnVH:L registers (Section 16.3.
Chapter 16 Timer/PWM Module (S08TPMV3) — TPMxCnVH:L = (TPMxMODH:L - 1) [SE110-TPM case 2] In this case, the TPM v3 produces almost 100% duty cycle. Instead, the TPM v2 produces 0% duty cycle. — TPMxCnVH:L is changed from 0x0000 to a non-zero value [SE110-TPM case 3 and 5] In this case, the TPM v3 waits for the start of a new PWM period to begin using the new duty cycle setting. Instead, the TPM v2 changes the channel output at the middle of the current PWM period (when the count reaches 0x0000).
Chapter 17 Development Support 17.1 Introduction Development support systems in the HCS08 include the background debug controller (BDC) and the on-chip debug module (DBG). The BDC provides a single-wire debug interface to the target MCU that provides a convenient interface for programming the on-chip FLASH and other nonvolatile memories.
Chapter 17 Development Support 17.1.
Chapter 17 Development Support • Non-intrusive commands can be executed at any time even while the user’s program is running. Non-intrusive commands allow a user to read or write MCU memory locations or access status and control registers within the background debug controller. Typically, a relatively simple interface pod is used to translate commands from a host computer into commands for the custom serial interface to the single-wire background debug system.
Chapter 17 Development Support When no debugger pod is connected to the 6-pin BDM interface connector, the internal pullup on BKGD chooses normal operating mode. When a debug pod is connected to BKGD it is possible to force the MCU into active background mode after reset. The specific conditions for forcing active background depend upon the HCS08 derivative (refer to the introduction to this Development Support section).
Chapter 17 Development Support Figure 17-2 shows an external host transmitting a logic 1 or 0 to the BKGD pin of a target HCS08 MCU. The host is asynchronous to the target so there is a 0-to-1 cycle delay from the host-generated falling edge to where the target perceives the beginning of the bit time. Ten target BDC clock cycles later, the target senses the bit level on the BKGD pin.
Chapter 17 Development Support Figure 17-3 shows the host receiving a logic 1 from the target HCS08 MCU. Because the host is asynchronous to the target MCU, there is a 0-to-1 cycle delay from the host-generated falling edge on BKGD to the perceived start of the bit time in the target MCU. The host holds the BKGD pin low long enough for the target to recognize it (at least two target BDC cycles).
Chapter 17 Development Support Figure 17-4 shows the host receiving a logic 0 from the target HCS08 MCU. Because the host is asynchronous to the target MCU, there is a 0-to-1 cycle delay from the host-generated falling edge on BKGD to the start of the bit time as perceived by the target MCU. The host initiates the bit time but the target HCS08 finishes it.
Chapter 17 Development Support 17.2.3 BDC Commands BDC commands are sent serially from a host computer to the BKGD pin of the target HCS08 MCU. All commands and data are sent MSB-first using a custom BDC communications protocol. Active background mode commands require that the target MCU is currently in the active background mode while non-intrusive commands may be issued at any time whether the target MCU is in active background mode or running a user application program.
Chapter 17 Development Support Table 17-1. BDC Command Summary Command Mnemonic 1 Active BDM/ Non-intrusive Coding Structure Description SYNC Non-intrusive n/a1 Request a timed reference pulse to determine target BDC communication speed ACK_ENABLE Non-intrusive D5/d Enable acknowledge protocol. Refer to Freescale document order no. HCS08RMv1/D. ACK_DISABLE Non-intrusive D6/d Disable acknowledge protocol. Refer to Freescale document order no. HCS08RMv1/D.
Chapter 17 Development Support The SYNC command is unlike other BDC commands because the host does not necessarily know the correct communications speed to use for BDC communications until after it has analyzed the response to the SYNC command. To issue a SYNC command, the host: • Drives the BKGD pin low for at least 128 cycles of the slowest possible BDC clock (The slowest clock is normally the reference oscillator/64 or the self-clocked rate/64.
Chapter 17 Development Support 17.3 On-Chip Debug System (DBG) Because HCS08 devices do not have external address and data buses, the most important functions of an in-circuit emulator have been built onto the chip with the MCU. The debug system consists of an 8-stage FIFO that can store address or data bus information, and a flexible trigger system to decide when to capture bus information and what information to capture.
Chapter 17 Development Support the host must perform ((8 – CNT) – 1) dummy reads of the FIFO to advance it to the first significant entry in the FIFO. In most trigger modes, the information stored in the FIFO consists of 16-bit change-of-flow addresses. In these cases, read DBGFH then DBGFL to get one coherent word of information out of the FIFO. Reading DBGFL (the low-order byte of the FIFO data port) causes the FIFO to shift so the next word of information is available at the FIFO data port.
Chapter 17 Development Support A force-type breakpoint waits for the current instruction to finish and then acts upon the breakpoint request. The usual action in response to a breakpoint is to go to active background mode rather than continuing to the next instruction in the user application program. The tag vs. force terminology is used in two contexts within the debug module. The first context refers to breakpoint requests from the debug module to the CPU.
Chapter 17 Development Support A-Only — Trigger when the address matches the value in comparator A A OR B — Trigger when the address matches either the value in comparator A or the value in comparator B A Then B — Trigger when the address matches the value in comparator B but only after the address for another cycle matched the value in comparator A. There can be any number of cycles after the A match and before the B match.
Chapter 17 Development Support 17.3.6 Hardware Breakpoints The BRKEN control bit in the DBGC register may be set to 1 to allow any of the trigger conditions described in Section 17.3.5, “Trigger Modes,” to be used to generate a hardware breakpoint request to the CPU. TAG in DBGC controls whether the breakpoint request will be treated as a tag-type breakpoint or a force-type breakpoint. A tag breakpoint causes the current opcode to be marked as it enters the instruction queue.
Chapter 17 Development Support 17.4.1.1 BDC Status and Control Register (BDCSCR) This register can be read or written by serial BDC commands (READ_STATUS and WRITE_CONTROL) but is not accessible to user programs because it is not located in the normal memory map of the MCU. 7 R 6 5 4 3 BKPTEN FTS CLKSW BDMACT ENBDM 2 1 0 WS WSF DVF W Normal Reset 0 0 0 0 0 0 0 0 Reset in Active BDM: 1 1 0 0 1 0 0 0 = Unimplemented or Reserved Figure 17-5.
Chapter 17 Development Support Table 17-2. BDCSCR Register Field Descriptions (continued) Field Description 2 WS Wait or Stop Status — When the target CPU is in wait or stop mode, most BDC commands cannot function. However, the BACKGROUND command can be used to force the target CPU out of wait or stop and into active background mode where all BDC commands work.
Chapter 17 Development Support R 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 BDFR1 W Reset 0 0 0 0 0 0 0 0 = Unimplemented or Reserved 1 BDFR is writable only through serial background mode debug commands, not from user programs. Figure 17-6. System Background Debug Force Reset Register (SBDFR) Table 17-3.
Chapter 17 Development Support 17.4.3.5 Debug FIFO High Register (DBGFH) This register provides read-only access to the high-order eight bits of the FIFO. Writes to this register have no meaning or effect. In the event-only trigger modes, the FIFO only stores data into the low-order byte of each FIFO word, so this register is not used and will read 0x00. Reading DBGFH does not cause the FIFO to shift to the next word.
Chapter 17 Development Support 17.4.3.7 Debug Control Register (DBGC) This register can be read or written at any time. 7 6 5 4 3 2 1 0 DBGEN ARM TAG BRKEN RWA RWAEN RWB RWBEN 0 0 0 0 0 0 0 0 R W Reset Figure 17-7. Debug Control Register (DBGC) Table 17-4. DBGC Register Field Descriptions Field Description 7 DBGEN Debug Module Enable — Used to enable the debug module. DBGEN cannot be set to 1 if the MCU is secure.
Chapter 17 Development Support 17.4.3.8 Debug Trigger Register (DBGT) This register can be read any time, but may be written only if ARM = 0, except bits 4 and 5 are hard-wired to 0s. 7 6 TRGSEL BEGIN 0 0 R 5 4 0 0 3 2 1 0 TRG3 TRG2 TRG1 TRG0 0 0 0 0 W Reset 0 0 = Unimplemented or Reserved Figure 17-8. Debug Trigger Register (DBGT) Table 17-5.
Chapter 17 Development Support 17.4.3.9 Debug Status Register (DBGS) This is a read-only status register. R 7 6 5 4 3 2 1 0 AF BF ARMF 0 CNT3 CNT2 CNT1 CNT0 0 0 0 0 0 0 0 0 W Reset = Unimplemented or Reserved Figure 17-9. Debug Status Register (DBGS) Table 17-6. DBGS Register Field Descriptions Field Description 7 AF Trigger Match A Flag — AF is cleared at the start of a debug run and indicates whether a trigger match A condition was met since arming.
Appendix A Electrical Characteristics A.1 Introduction This section contains electrical and timing specifications for the MC9S08SH32 Series of microcontrollers available at the time of publication. A.2 Parameter Classification The electrical parameters shown in this supplement are guaranteed by various methods. To give the customer a better understanding the following classification is used and the parameters are tagged accordingly in the tables where appropriate: Table A-1.
Appendix A Electrical Characteristics inputs are tied to an appropriate logic voltage level (for instance, either VSS or VDD) or the programmable pull-up resistor associated with the pin is enabled. Table A-2. Absolute Maximum Ratings Rating Symbol Value Unit Supply voltage VDD –0.3 to +5.8 V Maximum current into VDD IDD 120 mA Digital input voltage VIn –0.3 to VDD + 0.
Appendix A Electrical Characteristics A.4 Thermal Characteristics This section provides information about operating temperature range, power dissipation, and package thermal resistance. Power dissipation on I/O pins is usually small compared to the power dissipation in on-chip logic and voltage regulator circuits, and it is user-determined rather than being controlled by the MCU design.
Appendix A Electrical Characteristics The average chip-junction temperature (TJ) in °C can be obtained from: TJ = TA + (PD × θJA) Eqn. A-1 where: TA = Ambient temperature, °C θJA = Package thermal resistance, junction-to-ambient, °C/W PD = Pint + PI/O Pint = IDD × VDD, Watts — chip internal power PI/O = Power dissipation on input and output pins — user determined For most applications, PI/O << Pint and can be neglected.
Appendix A Electrical Characteristics A.5 ESD Protection and Latch-Up Immunity Although damage from electrostatic discharge (ESD) is much less common on these devices than on early CMOS circuits, normal handling precautions should be used to avoid exposure to static discharge. Qualification tests are performed to ensure that these devices can withstand exposure to reasonable levels of static without suffering any permanent damage.
Appendix A Electrical Characteristics A.6 DC Characteristics This section includes information about power supply requirements and I/O pin characteristics. Table A-6. DC Characteristics Num C 1 2 3 4 5 6 7 Characteristic Symbol — Operating Voltage Condition All I/O pins, P low-drive strength C Output high VOH C voltage Typ1 2.7 VDD C Min Max Unit 5.5 V 5 V, ILoad = –4 mA VDD – 1.5 — — 5 V, ILoad = –2 mA VDD – 0.8 — — 3 V, ILoad = –1 mA VDD – 0.
Appendix A Electrical Characteristics Table A-6. DC Characteristics (continued) Num C 14 15 Characteristic Min Typ1 Max Unit VRAM — 0.6 1.0 V VPOR 0.9 1.4 2.0 V tPOR 10 — — μs 3.9 4.0 4.0 4.1 4.1 4.2 V 2.48 2.54 2.56 2.62 2.64 2.70 V 4.5 4.6 4.6 4.7 4.7 4.8 V 4.2 4.3 4.3 4.4 4.4 4.5 V 2.84 2.90 2.92 2.98 3.00 3.06 V 2.66 2.72 2.74 2.80 2.82 2.88 V 5V — 100 — 3V — 60 — 1.18 1.202 1.
Appendix A Electrical Characteristics 2 1.0 125˚C 25˚C –40˚C 0.8 VOL (V) VOL (V) 1.5 1 0.5 0 125˚C 25˚C –40˚C Max 1.5V@25mA Max 0.8V@5mA 0.6 0.4 0.2 0 5 10 15 IOL (mA) a) VDD = 5V, High Drive 20 0 25 0 2 4 6 IOL (mA) b) VDD = 3V, High Drive 8 10 Figure A-1. Typical VOL vs IOL, High Drive Strength 2 1.0 125˚C 25˚C –40˚C 0.8 VOL (V) VOL (V) 1.5 1 0.5 0 125˚C 25˚C –40˚C Max 1.5V@4mA Max 0.8V@1mA 0.6 0.4 0.2 0 1 2 3 IOL (mA) a) VDD = 5V, Low Drive 4 5 0 0 0.4 0.8 1.
Appendix A Electrical Characteristics 2 1.0 125˚C 25˚C –40˚C 0.8 VDD – VOH (V) VDD – VOH (V) 1.5 1 0.5 0 125˚C 25˚C –40˚C Max 1.5V@20mA Max 0.8V@5mA 0.6 0.4 0.2 0 –5 –10 –15 –20 IOH (mA) a) VDD = 5V, High Drive 0 –25 0 –2 –4 –6 –8 IOH (mA) b) VDD = 3V, High Drive –10 Figure A-3. Typical VDD – VOH vs IOH, High Drive Strength 2 1.0 125˚C 25˚C –40˚C 0.8 VDD – VOH (V) VDD – VOH (V) 1.5 1 0.5 0 125˚C 25˚C –40˚C Max 1.5V@4mA Max 0.8V@1mA 0.6 0.4 0.
Appendix A Electrical Characteristics A.7 Supply Current Characteristics This section includes information about power supply current in various operating modes. Table A-7. Supply Current Characteristics Num C C 1 2 C P C C 3 C Parameter Symbol 3 Run supply current measured at (CPU clock = 4 MHz, fBus = 2 MHz) RIDD Run supply current3 measured at (CPU clock = 16 MHz, fBus = 8 MHz) RIDD 4 Run supply current measured at (CPU clock = 32 MHz, fBus = 16MHz) RIDD VDD (V) Typ1 Max2 5 1.
Appendix A Electrical Characteristics Table A-7. Supply Current Characteristics (continued) Num C Parameter Symbol VDD (V) Typ1 Max2 Unit Stop2 mode supply current 5 C –40°C (C and M suffix) 0.94 – P 25°C (All parts) 1.25 – P5 85°C (C suffix only) 13.4 30 P5 125°C (M suffix only) 65 120 C –40°C (C and Msuffix) 0.83 – P 25°C (All parts) 1.1 – 5 85°C (C suffix only) 11.
Appendix A Electrical Characteristics 12 FEI FBELP 10 Run IDD (mA) 8 6 4 2 0 0 1 2 4 8 20 16 fbus (MHz) Figure A-5. Typical Run IDD vs. Bus Frequency (VDD = 5V) 6 RUN 5 Run IDD (μA) 4 3 WAIT 2 1 0 –40 0 25 Temperature (˚C) 85 105 125 Figure A-6. Typical Run and Wait IDD vs. Temperature (VDD = 5V; fbus = 8MHz) MC9S08SH32 Series Data Sheet, Rev.
Appendix A Electrical Characteristics 90 80 STOP2 STOP3 70 60 STOP IDD (μA) 50 40 30 20 10 0 –40 0 25 Temperature (˚C) 85 105 125 Figure A-7. Typical Stop IDD vs. Temperature (VDD = 5V) MC9S08SH32 Series Data Sheet, Rev.
Appendix A Electrical Characteristics A.8 External Oscillator (XOSC) Characteristics Table A-8. Oscillator Electrical Specifications (Temperature Range = –40 to 125°C Ambient) Num C Rating Symbol Min Typ1 Max Unit flo 32 — 38.
Appendix A Electrical Characteristics A.9 Internal Clock Source (ICS) Characteristics Table A-9. ICS Frequency Specifications (Temperature Range = –40 to 125°C Ambient) Num C Rating Symbol Min Typical Max Unit Internal reference frequency — factory trimmed at VDD = 5 V and temperature = 25°C fint_ft — 31.25 — kHz 1 P 2 T Internal reference frequency — untrimmed1 fint_ut 25 36 41.66 kHz 3 P Internal reference frequency — trimmed fint_t 31.25 — 39.
Deviation from Trimmed Frequency Appendix A Electrical Characteristics +2% +1% 0 –1% –2% –40 0 25 Temperature (˚C) 85 105 125 Figure A-8. Typical Frequency Deviation vs Temperature (ICS Trimmed to 16MHz bus@25˚C, 5V, FEI)1 A.10 Analog Comparator (ACMP) Electricals Table A-10. Analog Comparator Electrical Specifications Num C 1 — 2 C/T 3 Rating Symbol Min Typical Max Unit VDD 2.7 — 5.5 V Supply current (active) IDDAC — 20 35 μA D Analog input voltage VAIN VSS – 0.
Appendix A Electrical Characteristics A.11 ADC Characteristics Table A-11. ADC Operating Conditions Symb Min Typ1 Max Unit VDDAD 2.7 — 5.5 V Input Voltage VADIN VREFL — VREFH V 3 Input Capacitance CADIN — 4.5 5.5 pF 4 Input Resistance RADIN — 3 5 kΩ — — — — 5 10 — — 10 0.4 — 8.0 0.4 — 4.0 Num Characteristic 1 Supply voltage 2 5 Conditions Absolute Analog Source Resistance 8 bit mode (all valid fADCK) 6 7 8 1 ADC Conversion Clock Freq.
Appendix A Electrical Characteristics Table A-12. ADC Characteristics C Symb Min Typ1 Max Unit Comment ADLPC=1 ADLSMP=1 ADCO=1 T IDD + IDDAD — 133 — μA ADC current only ADLPC=1 ADLSMP=0 ADCO=1 T IDD + IDDAD — 218 — μA ADC current only ADLPC=0 ADLSMP=1 ADCO=1 T IDD + IDDAD — 327 — μA ADC current only ADLPC=0 ADLSMP=0 ADCO=1 P IDD + IDDAD — 0.582 1 mA ADC current only ADC asynchronous clock source High speed (ADLPC=0) P fADACK 2 3.3 5 MHz 1.25 2 3.
Appendix A Electrical Characteristics Table A-12. ADC Characteristics (continued) Characteristic Conditions C Symb Min Typ1 Max Unit P EZS — ±0.5 ±1.5 LSB2 — ±0.5 ±0.5 — ±1.5 ±2.5 — ±0.5 ±0.7 0 ±0.5 ±1 0 ±0.5 ±0.5 0 ±1.0 ±1.5 0 ±0.5 ±0.5 — — ±0.5 — — ±0.5 0 ±0.2 ±2.5 0 ±0.1 ±1 — 3.266 — — 3.638 — — 1.
Appendix A Electrical Characteristics A.12 AC Characteristics This section describes ac timing characteristics for each peripheral system. A.12.1 Control Timing Table A-13.
Appendix A Electrical Characteristics tIHIL IRQ/Pin Interrupts IRQ/ Pin Interrupts tILIH Figure A-11. IRQ/Pin Interrupt Timing MC9S08SH32 Series Data Sheet, Rev.
Appendix A Electrical Characteristics A.12.2 TPM/MTIM Module Timing Synchronizer circuits determine the shortest input pulses that can be recognized or the fastest clock that can be used as the optional external source to the timer counter. These synchronizers operate from the current bus rate clock. Table A-14.
Appendix A Electrical Characteristics A.12.3 SPI Table A-15 and Figure A-14 through Figure A-17 describe the timing requirements for the SPI system. Table A-15.
Appendix A Electrical Characteristics SS1 (OUTPUT) 1 2 SCK (CPOL = 0) (OUTPUT) 3 5 4 SCK (CPOL = 1) (OUTPUT) 5 4 6 MISO (INPUT) 7 MSB IN2 BIT 6 . . . 1 10 MOSI (OUTPUT) LSB IN 10 MSB OUT2 11 BIT 6 . . . 1 LSB OUT NOTES: 1. SS output mode (MODFEN = 1, SSOE = 1). 2. LSBF = 0. For LSBF = 1, bit order is LSB, bit 1, ..., bit 6, MSB. Figure A-14.
Appendix A Electrical Characteristics SS (INPUT) 3 1 SCK (CPOL = 0) (INPUT) 5 4 2 SCK (CPOL = 1) (INPUT) 5 4 8 MISO (OUTPUT) 11 10 BIT 6 . . . 1 MSB OUT SLAVE SLAVE LSB OUT SEE NOTE 7 6 MOSI (INPUT) 9 BIT 6 . . . 1 MSB IN LSB IN NOTE: 1. Not defined but normally MSB of character just received Figure A-16. SPI Slave Timing (CPHA = 0) SS (INPUT) 1 3 2 SCK (CPOL = 0) (INPUT) 5 4 SCK (CPOL = 1) (INPUT) 5 4 10 MISO (OUTPUT) SEE NOTE 8 MOSI (INPUT) SLAVE 11 MSB OUT 6 BIT 6 . . .
Appendix A Electrical Characteristics A.13 Flash Specifications This section provides details about program/erase times and program-erase endurance for the Flash memory. Program and erase operations do not require any special power sources other than the normal VDD supply. For more detailed information about program/erase operations, see the Memory section. Table A-16.
Appendix A Electrical Characteristics A.14 EMC Performance Electromagnetic compatibility (EMC) performance is highly dependant on the environment in which the MCU resides. Board design and layout, circuit topology choices, location and characteristics of external components as well as MCU software operation all play a significant role in EMC performance.
Appendix A Electrical Characteristics Table A-18. Conducted Susceptibility, EFT/B Parameter Symbol Conducted susceptibility, electrical fast transient/burst (EFT/B) 1 VCS_EFT Conditions VDD = TBD TA = +25oC package type TBD fOSC/fBUS TBD crystal TBD bus Result Amplitude1 (Min) A TBD B TBD C TBD D TBD Unit kV Data based on qualification test results. Not tested in production. The susceptibility performance classification is described in Table A-19. Table A-19.
Appendix B Ordering Information and Mechanical Drawings B.1 Ordering Information This section contains ordering information for MC9S08SH32 and MC9S08SH16 devices. Jennifer Table B-1. Device Numbering System Flash 1 2 Available Packages2 Memory Device Number1 RAM 28-Pin 20-Pin 16-Pin 28 TSSOP 28 SOIC 20 TSSOP 16 TSSOP MC9S08SH32 32 K 1024 B MC9S08SH16 16 1024 B See Table 1-1for a complete description of modules included on each device. See Table B-2 for package information. B.1.
Appendix B Ordering Information and Mechanical Drawings B.2 Mechanical Drawings The following pages are mechanical specifications for MC9S08SH32 Series package options. See Table B-2 for the document number for each package type. is Table B-2. Package Information Pin Count Type Designator Document No. 28 SOIC WL 98ASB42345B 28 TSSOP TL 98ARS23923W 20 TSSOP TJ 98ASH70169A 16 TSSOP TG 98ASH70247A MC9S08SH32 Series Data Sheet, Rev.
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