Datasheet

MC9S08QE8 Series Data Sheet, Rev. 8
Electrical Characteristics
Freescale Semiconductor22
3.10.3 SPI Timing
Table 14 and Figure 19 through Figure 22 describe the timing requirements for the SPI system.
Table 14. SPI Timing
No. C Function Symbol Min Max Unit
—D
Operating frequency
Master
Slave
f
op
f
Bus
/2048
0
f
Bus
/2
f
Bus
/4
Hz
1D
SPSCK period
Master
Slave
t
SPSCK
2
4
2048
—
t
cyc
t
cyc
2D
Enable lead time
Master
Slave
t
Lead
12
1
—
—
t
SPSCK
t
cyc
3D
Enable lag time
Master
Slave
t
Lag
12
1
—
—
t
SPSCK
t
cyc
4D
Clock (SPSCK) high or low time
Master
Slave
t
WSPSCK
t
cyc
–30
t
cyc
– 30
1024 t
cyc
—
ns
ns
5D
Data setup time (inputs)
Master
Slave
t
SU
15
15
—
—
ns
ns
6D
Data hold time (inputs)
Master
Slave
t
HI
0
25
—
—
ns
ns
7 D Slave access time t
a
—1t
cyc
8 D Slave MISO disable time t
dis
—1t
cyc
9D
Data valid (after SPSCK edge)
Master
Slave
t
v
—
—
25
25
ns
ns
10 D
Data hold time (outputs)
Master
Slave
t
HO
0
0
—
—
ns
ns
11 D
Rise time
Input
Output
t
RI
t
RO
—
—
t
cyc
– 25
25
ns
ns
12 D
Fall time
Input
Output
t
FI
t
FO
—
—
t
cyc
– 25
25
ns
ns