Datasheet

Electrical Characteristics
MC9S08QE8 Series Data Sheet, Rev. 8
Freescale Semiconductor 19
Figure 14. Deviation of DCO Output from Trimmed Frequency (20 MHz, 3.0 V)
7C
Resolution of trimmed DCO output frequency at fixed
voltage and temperature (not using FTRIM)
f
dco_res_t
— 0.2 0.4
%f
dco
8C
Total deviation of DCO output from trimmed frequency
3
Over full voltage and temperature range
Over fixed voltage and temperature range of 0 to 70 C
f
dco_t
— –1.0 to 0.5
0.5
2
1
%f
dco
10 C
FLL acquisition time
4
t
Acquire
—— 1ms
11 C
Long term jitter of DCO output clock (averaged over 2-ms
interval)
5
C
Jitter
—0.020.2
%f
dco
1
Data in Typical column was characterized at 3.0 V, 25 C or is typical recommended value.
2
The resulting bus clock frequency should not exceed the maximum specified bus clock frequency of the device.
3
This parameter is characterized and not tested on each device.
4
This specification applies to any time the FLL reference source or reference divider is changed, trim value changed or
changing from FLL disabled (FBELP, FBILP) to FLL enabled (FEI, FEE, FBE, FBI). If a crystal/resonator is being used
as the reference, this specification assumes it is already running.
5
Jitter is the average deviation from the programmed frequency measured over the specified interval at maximum f
Bus
.
Measurements are made with the device powered by filtered supplies and clocked by a stable external clock signal. Noise
injected into the FLL circuitry via V
DD
and V
SS
and variation in crystal oscillator frequency increase the C
Jitter
percentage
for a given interval.
Table 11. ICS Frequency Specifications (Temperature Range = –40 to 85C Ambient) (continued)
Num C Characteristic Symbol Min. Typical
1
Max. Unit
TBD
-2.00%
-1.50%
-1.00%
-0.50%
0.00%
0.50%
1.00%
-60 -40 -20 0 20 40 60 80 100 120
Temperature
Deviation (%)