Datasheet

MC9S08QE32 Series MCU Data Sheet, Rev. 7
Pin Assignments
Freescale Semiconductor8
19 17 PTD6 KBI2P6
20 18 PTD5 KBI2P5
21 19 13 15 PTC1 TPM3CH1
22 20 14 16 PTC0 TPM3CH0
23 21 15 17 PTB3 KBI1P7 MOSI
2
ADP7
24 22 16 18 PTB2 KBI1P6 SPSCK
2
ADP6
25 23 17 19 PTB1 KBI1P5 TxD1 ADP5
26 24 18 20 PTB0 KBI1P4 RxD1 ADP4
27 25 19 21 PTA7 TPM2CH2 ADP9
28 26 20 22 PTA6 TPM1CH2 ADP8
29———PTE4
30 27 V
DD
31 28 V
SS
32 29 PTD4 KBI2P4
33 30 21 PTD3 KBI2P3
34 31 22 PTD2 KBI2P2
35 32 23 23 PTA3 KBI1P3 SCL
1
ADP3
36 33 24 24 PTA2 KBI1P2 SDA
1
ADP2
37 34 25 25 PTA1 KBI1P1 TPM2CH0 ADP1
3
ACMP1
3
38 35 26 26 PTA0 KBI1P0 TPM1CH0 ADP0
3
ACMP1+
3
39 36 27 27 PTC7 TxD2 ACMP2–
40 37 28 28 PTC6 RxD2 ACMP2+
41 PTE3 SS
2
42 38 PTE2 MISO
2
43 39 PTE1 MOSI
2
44 40 PTE0 TPM2CLK SPSCK
2
45 41 29 1 PTC5 TPM3CH5 ACMP2O
46 42 30 2 PTC4 TPM3CH4
47 43 31 3 PTA5 IRQ TPM1CLK RESET
48 44 32 4 PTA4 ACMP1O BKGD MS
1
IIC pins, SCL and SDA can be repositioned using IICPS in SOPT2; default reset
locations are PTA3 and PTA2.
2
SPI pins (SS, MISO, MOSI, and SPSCK) can be repositioned using SPIPS in SOPT2.
Default locations are PTB5, PTB4, PTB3, and PTB2.
3
If ADC and ACMP1 are enabled, both modules will have access to the pin.
Table 1. MC9S08QE32 Series Pin Assignment by Package and Pin Sharing Priority (continued)
Pin Number <-- Lowest Priority --> Highest
48 44 32 28 Port Pin Alt 1 Alt 2 Alt 3 Alt 4