Datasheet

Freescale Semiconductor
Data Sheet: Technical Data
An Energy Efficient Solution by Freescale
Document Number: MC9S08QE32
Rev. 7, 9/2011
© Freescale Semiconductor, Inc., 2008-2011. All rights reserved.
This document contains information on a product under development. Freescale reserves the
right to change or discontinue this product without notice.
MC9S08QE32
MC9S08QE32 Series
Covers: MC9S08QE32 and
MC9S08QE16
48-QFN
Case 1314
7 mm 7 mm
32-LQFP
Case 873A
7 mm 7 mm
44-LQFP
Case 824D
10 mm 10 mm
28-SOIC
Case 751F
32-QFN
Case 1582
5 mm 5 mm
Features
8-Bit HCS08 Central Processor Unit (CPU)
Up to 50.33 MHz HCS08 CPU at 3.6 V to 2.4 V, 40 MHz CPU at 2.4
V to 2.1 V and 20 MHz CPU at 2.1 V to 1.8 V across temperature
range of –40 °C to 85 °C
HC08 instruction set with added BGND instruction
Support for up to 32 interrupt/reset sources
•On-Chip Memory
Flash read/program/erase over full operating voltage and
temperature
Random-access memory (RAM)
Security circuitry to prevent unauthorized access to RAM and flash
contents
Power-Saving Modes
Two very low power stop modes
Reduced power wait mode
Peripheral clock enable register can disable clocks to unused
modules, thereby reducing currents; allows clocks to remain enabled
to specific peripherals in stop3 mode.
Very low power external oscillator that can be used in run, wait, and
stop modes to provide accurate clock source to real time counter.
–6 s typical wakeup time from stop3 mode
Clock Source Options
Oscillator (XOSCVLP) — Loop-control Pierce oscillator; crystal or
ceramic resonator range of 31.25 kHz to 38.4 kHz or 1 MHz to 16
MHz
Internal clock source (ICS) — Internal clock source module
containing a frequency-locked-loop (FLL) controlled by internal or
external reference; precision trimming of internal reference allows
0.2% resolution and 2% deviation over temperature and voltage;
supports CPU frequencies from
4 kHz to 50.33 MHz.
System Protection
Watchdog computer operating properly (COP) reset with option to
run from dedicated 1 kHz internal clock source or bus clock.
Low-voltage warning with interrupt.
Low-voltage detection with reset or interrupt
Selectable trip points.
Illegal opcode detection with reset
Illegal address detection with reset
Flash block protection
Development Support
Single-wire background debug interface
Breakpoint capability to allow single breakpoint setting during
in-circuit debugging (plus three breakpoints in on-chip debug
module)
On-chip in-circuit emulator (ICE) debug module containing three
comparators and nine trigger modes. Eight deep FIFO for storing
change-of-flow addresses and event-only data. Debug module
supports both tag and force breakpoints
Peripherals
ADC — 10-channel, 12-bit resolution; 2.5s conversion time;
automatic compare function; 1.7 mV/C temperature sensor;
internal bandgap reference channel; operation in stop3; fully
functional from 3.6 V to 1.8 V
ACMPx — Two analog comparators with selectable interrupt on
rising, falling, or either edge of comparator output; compare option
to fixed internal bandgap reference voltage; outputs can be
optionally routed to TPM module; operation in stop3
SCIx — Two serial communications interface modules with
optional 13-bit break. Full duplex non-return to zero (NRZ); LIN
master extended break generation; LIN slave extended break
detection; wake on active edge.
SPI— One serial peripheral interface; full-duplex or single-wire
bidirectional; double-buffered transmit and receive; master or
slave mode; MSB-first or LSB-first shifting
IIC — One IIC; up to 100 kbps with maximum bus loading;
multi-master operation; programmable slave address; interrupt
driven byte-by-byte data transfer; supports broadcast mode and
10-bit addressing
TPMx — One 6-channel (TPM3) and two 3-channel (TPM1 and
TPM2); selectable input capture, output compare, or buffered
edge- or center-aligned PWM on each channel;
RTC — (Real-time counter) 8-bit modulus counter with binary or
decimal based prescaler; external clock source for precise time
base, time-of-day, calendar or task scheduling functions; free
running on-chip low power oscillator (1 kHz) for cyclic wake-up
without external components; runs in all MCU modes
Input/Output
40 GPIOs, including 1 output-only pin and 1 input-only pin
16 KBI interrupts with selectable polarity
Hysteresis and configurable pull up device on all input pins;
Configurable slew rate and drive strength on all output pins.
Package Options
48-pin QFN, 44-pin LQFP, 32-pin LQFP/QFN, 28-pin SOIC

Summary of content (32 pages)