Datasheet

Chapter 5 Resets, Interrupts, and General System Control
MC9S08QD4 Series MCU Data Sheet, Rev. 6
56 Freescale Semiconductor
5.6 Low-Voltage Detect (LVD) System
The MC9S08QD4 series includes a system to protect against low voltage conditions in order to protect
memory contents and control MCU system states during supply voltage variations. The system is
comprised of a power-on reset (POR) circuit and an LVD circuit with a user selectable trip voltage, either
high (V
LVDH
) or low (V
LVDL
). The LVD circuit is enabled when LVDE in SPMSC1 is high and the trip
voltage is selected by LVDV in SPMSC2. The LVD is disabled upon entering any of the stop modes unless
LVDSE is set in SPMSC1. If LVDSE and LVDE are both set, then the MCU cannot enter stop1 or stop2,
and the current consumption in stop3 with the LVD enabled will be greater.
Table 5-2. Vector Summary
Vector
Priority
Vector
Number
Address
(High:Low)
Vector Name Module Source Enable Description
Lower
Higher
31
through
24
0xFFC0:FFC1
through
0xFFCE:FFCF
Unused Vector Space
(available for user program)
23 0xFFD0:FFD1 Vrti
System
control
RTIF RTIE Real-time interrupt
22 0xFFD2:FFD3
21 0xFFD4:FFD5
20 0xFFD6:FFD7
19 0xFFD8:FFD9 Vadc1 ADC1 COCO AIEN ADC1
18 0xFFDA:FFDB Vkeyboard1 KBI1 KBF KBIE Keyboard pins
17 0xFFDC:FFDD
16 0xFFDE:FFDF
15 0xFFE0:FFE1
14 0xFFE2:FFE3
13 0xFFE4:FFE5
12 0xFFE6:FFE7
11 0xFFE8:FFE9
10 0xFFEA:FFEB Vtpm2ovf TPM2 TOF TOIE TPM2 overflow
9 0xFFEC:FFED
8 0xFFEE:FFEF Vtpm2ch0 TPM2 CH0F CH0IE TPM2 channel 0
7 0xFFF0:FFF1 Vtpm1ovf TPM1 TOF TOIE TPM1 overflow
6 0xFFF2:FFF3 Vtpm1ch1 TPM1 CH1F CH1IE TPM1 channel 1
5 0xFFF4:FFF5 Vtpm1ch0 TPM1 CH0F CH0IE TPM1 channel 0
4 0xFFF6:FFF7
3 0xFFF8:FFF9 Virq IRQ IRRQF IRQIE IRQ pin
2 0xFFFA:FFFB Vlvd
System
control
LVDF LVDIE Low voltage detect
1 0xFFFC:FFFD Vswi CPU
SWI
Instruction
Software interrupt
0 0xFFFE:FFFF Vreset
System
control
COP
LVD
RESET
pin
Illegal opcode
Illegal address
POR
COPE
LVDRE
RSTPE
Watchdog timer
Low-voltage detect
External pin
Illegal opcode
Illegal address
power-on-reset