Datasheet

Chapter 4 Memory Map and Register Definition
MC9S08QD4 Series MCU Data Sheet, Rev. 6
Freescale Semiconductor 41
Figure 4-3. Flash Burst Program Flowchart
4.5.5 Access Errors
An access error occurs whenever the command execution protocol is violated.
Any of the following specific actions will cause the access error flag (FACCERR) in FSTAT to be set.
FACCERR must be cleared by writing a 1 to FACCERR in FSTAT before any command can be
processed.
• Writing to a flash address before the internal flash clock frequency has been set by writing to the
FCDIV register
• Writing to a flash address while FCBEF is not set (A new command cannot be started until the
command buffer is empty.)
1
0
FCBEF ?
START
WRITE TO FLASH
TO BUFFER ADDRESS AND DATA
WRITE COMMAND TO FCMD
NO
YES
FPVIO OR
WRITE 1 TO FCBEF
TO LAUNCH COMMAND
AND CLEAR FCBEF
(2)
NO
YES
NEW BURST COMMAND ?
1
0
FCCF ?
ERROR EXIT
DONE
(2)
Wait at least four bus cycles before
checking FCBEF or FCCF.
1
0
FACCERR ?
CLEAR ERROR
FACCERR ?
WRITE TO FCDIV
(1)
(1)
Required only once
after reset.