Datasheet

Chapter 1 Device Overview
MC9S08QD4 Series MCU Data Sheet, Rev. 6
18 Freescale Semiconductor
1.3 System Clock Distribution
Figure 1-2 shows a simplified clock connection diagram. Some modules in the MCU have selectable clock
inputs as shown. The clock inputs to the modules indicate the clock(s) that are used to drive the module
function. All memory mapped registers associated with the modules are clocked with BUSCLK.
Figure 1-2. System Clock Distribution Diagram
Table 1-2. Versions of On-Chip Modules
Module Version
Analog-to-Digital Converter (ADC) 1
Central Processing Unit (CPU) 2
Internal Clock Source (ICS) 1
Keyboard Interrupt (KBI) 2
Timer Pulse-Width Modulator (TPM) 2
TPM1 TPM2
CPU
BDC
ADC
2
FLASH
3
ICS
ICSOUT
÷2
SYSTEM CONTROL LOGIC
BUSCLK
ICSLCLK
1
RTI
1
ICSLCLK is the alternate BDC clock source for the MC9S08QD4 series.
2
ADC has min. and max frequency requirements. See ADC chapter and Appendix A, “Electrical Characteristics.”
3
Flash has frequency requirements for program and erase operation.See Appendix A, “Electrical Characteristics.”
÷2
ICSFFCLK
COP
TCLK1 TCLK2
ICSIRCLK
FIXED FREQ CLOCK (XCLK)