Datasheet

Internal Clock Source (S08ICSV1)
MC9S08QD4 Series MCU Data Sheet, Rev. 6
128 Freescale Semiconductor
9.4 Functional Description
9.4.1 Operational Modes
Figure 9-7. Clock Switching Modes
The seven states of the ICS are shown as a state diagram and are described below. The arrows indicate the
allowed movements between the states.
9.4.1.1 FLL Engaged Internal (FEI)
FLL engaged internal (FEI) is the default mode of operation and is entered when all the following
conditions occur:
• CLKS bits are written to 00
• IREFS bit is written to 1
• RDIV bits are written to divide trimmed reference clock to be within the range of 31.25 kHz to
39.0625 kHz.
In FLL engaged internal mode, the ICSOUT clock is derived from the FLL clock, which is controlled by
the internal reference clock. The FLL loop will lock the frequency to 512 times the filter frequency, as
selected by the RDIV bits. The ICSLCLK is available for BDC communications, and the internal reference
clock is enabled.
FLL Bypassed
Internal Low
Power(FBILP)
IREFS=1
CLKS=00
Entered from any state
when MCU enters stop
FLL Engaged
Internal (FEI)
FLL Bypassed
Internal (FBI)
FLL Bypassed
External (FBE)
FLL Engaged
External (FEE)
FLL Bypassed
External Low
Power(FBELP)
IREFS=0
CLKS=00
IREFS=0
CLKS=10
BDM Enabled
or LP =0
Returns to state that was active
before MCU entered stop, unless
reset occurs while in stop.
IREFS=0
CLKS=10
BDM Disabled
and LP=1
IREFS=1
CLKS=01
BDM Enabled
or LP=0
IREFS=1
CLKS=01
BDM Disabled
and LP=1
Stop