MC9S08QD4 MC9S08QD2 S9S08QD4 S9S08QD2 Data Sheet HCS08 Microcontrollers MC9S08QD4 Rev. 6 10/2010 freescale.
MC9S08QD4 Series Features 8-Bit HCS08 Central Processor Unit (CPU) • • • • • 16 MHz HCS08 CPU (central processor unit) HC08 instruction set with added BGND instruction Background debugging system Breakpoint capability to allow single breakpoint setting during in-circuit debugging (plus two more breakpoints in on-chip debug module) Support for up to 32 interrupt/reset sources • Peripherals • • Memory • • • Flash read/program/erase over full operating voltage and temperature Flash size: — MC9S08QD4
MC9S08QD4 Data Sheet Covers: MC9S08QD4 MC9S08QD2 S9S08QD4 S9S08QD2 MC9S08QD4 Rev.
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List of Chapters Chapter 1 Device Overview ...................................................................... 15 Chapter 2 External Signal Description .................................................... 19 Chapter 3 Modes of Operation ................................................................. 25 Chapter 4 Memory Map and Register Definition .................................... 31 Chapter 5 Resets, Interrupts, and General System Control..................
Contents Section Number Title Page Chapter 1 Device Overview 1.1 1.2 1.3 Introduction .....................................................................................................................................15 Devices in the MC9S08QD4 Series ................................................................................................15 1.2.1 MCU Block Diagram ........................................................................................................
4.6 4.7 4.5.2 Program and Erase Times .................................................................................................37 4.5.3 Program and Erase Command Execution .........................................................................38 4.5.4 Burst Program Execution ..................................................................................................39 4.5.5 Access Errors ........................................................................................................
6.2 6.3 6.4 Pin Control — Pullup, Slew Rate and Drive Strength ....................................................................68 Pin Behavior in Stop Modes ............................................................................................................68 Parallel I/O Registers ......................................................................................................................69 6.4.1 Port A Registers ........................................................................
8.4 8.5 8.6 8.3.2 Status and Control Register 2 (ADCSC2) ......................................................................101 8.3.3 Data Result High Register (ADCRH) .............................................................................102 8.3.4 Data Result Low Register (ADCRL) ..............................................................................102 8.3.5 Compare Value High Register (ADCCVH) ....................................................................103 8.3.
9.5 Module Initialization ....................................................................................................................132 9.5.1 ICS Module Initialization Sequence ...............................................................................132 Chapter 10 Keyboard Interrupt (S08KBIV2) 10.1 Introduction ...................................................................................................................................135 10.1.1 Features ..............................
Chapter 12 Development Support 12.1 Introduction ...................................................................................................................................159 12.1.1 Forcing Active Background ............................................................................................159 12.1.2 Module Configuration .....................................................................................................159 12.1.3 Features ..................................................
Chapter 1 Device Overview 1.1 Introduction MC9S08QD4 series MCUs are members of the low-cost, high-performance HCS08 family of 8-bit microcontroller units (MCUs). All MCUs in the family use the enhanced HCS08 core and are available with a variety of modules, memory sizes, memory types, and package types. 1.
Chapter 1 Device Overview Table 1-1. Features by MCU and Package Consumer and Industrial Devices Feature MC9S08QD4 MC9S08QD2 Flash 4 KB 2 KB RAM 256 B 128 B ADC 4-ch, 10-bit Bus speed 8 MHz at 5 V Operating voltage 2.7 to 5.
Chapter 1 Device Overview 1.2.
Chapter 1 Device Overview Table 1-2. Versions of On-Chip Modules Module Version Analog-to-Digital Converter 1.3 (ADC) 1 Central Processing Unit (CPU) 2 Internal Clock Source (ICS) 1 Keyboard Interrupt (KBI) 2 Timer Pulse-Width Modulator (TPM) 2 System Clock Distribution Figure 1-2 shows a simplified clock connection diagram. Some modules in the MCU have selectable clock inputs as shown. The clock inputs to the modules indicate the clock(s) that are used to drive the module function.
Chapter 2 External Signal Description This chapter describes signals that connect to package pins. It includes pinout diagrams, table of signal properties, and detailed discussions of signals. 2.1 Device Pin Assignment Figure 2-1 shows the pin assignments for the 8-pin packages. PTA5/TPM2CH0I/IRQ/RESET 1 8 PTA0/KBI1P0/TPM1CH0/ADC1P0 PTA4/TPM2CH0O/BKGD/MS 2 7 PTA1/KBI1P1/TPM1CH1/ADC1P1 VDD 3 6 PTA2/KBI1P2/TCLK1/ADC1P2 VSS 4 5 PTA3/KBI1P3/TCLK2/ADC1P3 Figure 2-1. 8-Pin Packages 2.
Chapter 2 External Signal Description MC9S08QD4 VDD SYSTEM POWER + 5V CBLK + 10 μF PTA0/KBI1P0/TPM1CH0/ADC1P0 VDD CBY PTA1/KBI1P1/TPM1CH1/ADC1P1 PORT A 0.1 μF VSS PTA2/KBI1P2/TCLK1/ADC1P2 PTA3/KBI1P3/TCLK2/ADC1P3 PTA4/TPM2CH0O/BKGD/MS PTA5/TPM2CH0I/IRQ/RESET I/O AND PERIPHERAL INTERFACE TO APPLICATION SYSTEM BACKGROUND HEADER BKGD VDD NOTE 1 OPTIONAL MANUAL RESET ASYNCHRONOUS INTERRUPT INPUT RESET IRQ NOTE 2 NOTES: 1.
Chapter 2 External Signal Description 2.2.2 Oscillator Out of reset the MCU uses an internally generated clock provided by the internal clock source (ICS) module. The internal frequency is nominally 16 MHz and the default ICS settings will provide for a 4 MHz bus out of reset. For more information on the ICS, see the Internal Clock Source chapter. 2.2.3 Reset (Input Only) After a power-on reset (POR) into user mode, the PTA5/TPM2CH0I/IRQ/RESET pin defaults to a general-purpose input port pin, PTA5.
Chapter 2 External Signal Description Although the BKGD pin is a pseudo open-drain pin, the background debug communication protocol provides brief, actively driven, high speedup pulses to ensure fast rise times. Small capacitances from cables and the absolute value of the internal pullup device play almost no role in determining rise and fall times on the BKGD pin. 2.2.
Chapter 2 External Signal Description 2.2.5.2 Output Slew Rate Control Slew rate control can be enabled for each port pin by setting the corresponding bit in one of the slew rate control registers (PTxSEn). When enabled, slew control limits the rate at which an output can transition in order to reduce EMC emissions. Slew rate control has no effect on pins that are configured as inputs. 2.2.5.
Chapter 2 External Signal Description MC9S08QD4 Series MCU Data Sheet, Rev.
Chapter 3 Modes of Operation 3.1 Introduction The operating modes of the MC9S08QD4 series are described in this chapter. Entry into each mode, exit from each mode, and functionality while in each of the modes are described. 3.2 • • • 3.
Chapter 3 Modes of Operation After entering active background mode, the CPU is held in a suspended state waiting for serial background commands rather than executing instructions from the user’s application program. Background commands are of two types: • Non-intrusive commands, defined as commands that can be issued while the user program is running.
Chapter 3 Modes of Operation the CPU executes a STOP instruction, the MCU will not enter either of the stop modes and an illegal opcode reset is forced. The stop modes are selected by setting the appropriate bits in SPMSC2. HCS08 devices that are designed for low voltage operation (1.8V to 3.6V) also include stop1 mode. The MC9S08QD4 series does not include stop1 mode. Table 3-1 summarizes the behavior of the MCU in each of the stop modes. Table 3-1.
Chapter 3 Modes of Operation After waking up from stop2, the PPDF bit in SPMSC2 is set. This flag may be used to direct user code to go to a stop2 recovery routine. PPDF remains set and the I/O pin states remain latched until a logic 1 is written to PPDACK in SPMSC2. To maintain I/O state for pins that were configured as general-purpose I/O, the user must restore the contents of the I/O port registers, which have been saved in RAM, to the port registers before writing to the PPDACK bit.
Chapter 3 Modes of Operation Table 3-2. BDM Enabled Stop Mode Behavior Mode PPDC CPU, Digital Peripherals, Flash RAM ICS ADC1 Regulator I/O Pins RTI Stop3 0 Standby Standby Active Optionally on Active States held Optionally on 3.6.4 LVD Enabled in Stop Mode The LVD system is capable of generating either an interrupt or a reset when the supply voltage drops below the LVD voltage.
Chapter 3 Modes of Operation MC9S08QD4 Series MCU Data Sheet, Rev.
Chapter 4 Memory Map and Register Definition 4.1 MC9S08QD4 Series Memory Maps As shown in Figure 4-1, on-chip memory in the MC9S08QD4 series MCU consists of RAM, flash program memory for non-volatile data storage, and I/O and control/status registers.
Chapter 4 Memory Map and Register Definition 4.2 Reset and Interrupt Vector Assignments Table 4-1 shows address assignments for reset and interrupt vectors. The vector names shown in this table are the labels used in the Freescale Semiconductor-provided equate file for the MC9S08QD4 series. Table 4-1.
Chapter 4 Memory Map and Register Definition 4.3 Register Addresses and Bit Assignments The registers in the MC9S08QD4 series are divided into these groups: • Direct-page registers are located in the first 96 locations in the memory map; these are accessible with efficient direct addressing mode instructions. • High-page registers are used much less often, so they are located above 0x1800 in the memory map. This leaves more room in the direct page for more frequently used registers and RAM.
Chapter 4 Memory Map and Register Definition Table 4-2.
Chapter 4 Memory Map and Register Definition Table 4-3.
Chapter 4 Memory Map and Register Definition Table 4-4.
Chapter 4 Memory Map and Register Definition For compatibility with M68HC05 MCUs, the HCS08 resets the stack pointer to 0x00FF. In the MC9S08QD4 series, it is usually best to reinitialize the stack pointer to the top of the RAM so the direct page RAM can be used for frequently accessed RAM variables and bit-addressable program variables.
Chapter 4 Memory Map and Register Definition program and erase pulses. An integer number of these timing pulses is used by the command processor to complete a program or erase command. Table 4-5 shows program and erase times. The bus clock frequency and FCDIV determine the frequency of FCLK (fFCLK). The time for one cycle of FCLK is tFCLK = 1/fFCLK. The times are shown as a number of cycles of FCLK and as an absolute time for the case where tFCLK = 5 μs.
Chapter 4 Memory Map and Register Definition Aborting a command in this way sets the FACCERR access error flag which must be cleared before starting a new command. A strictly monitored procedure must be obeyed or the command will not be accepted. This minimizes the possibility of any unintended changes to the flash memory contents. The command complete flag (FCCF) indicates when a command is complete. The command sequence must be completed by clearing FCBEF to launch the command.
Chapter 4 Memory Map and Register Definition program command is issued, the charge pump is enabled and then remains enabled after completion of the burst program operation if these two conditions are met: • The next burst program command has been queued before the current program operation has completed. • The next sequential address selects a byte on the same physical row as the current byte being programmed. A row of flash memory consists of 64 bytes.
Chapter 4 Memory Map and Register Definition START 0 FACCERR ? 1 CLEAR ERROR WRITE TO FCDIV(1) FCBEF ? (1) Required only once after reset. 0 1 WRITE TO FLASH TO BUFFER ADDRESS AND DATA WRITE COMMAND TO FCMD WRITE 1 TO FCBEF TO LAUNCH COMMAND AND CLEAR FCBEF (2) FPVIO OR FACCERR ? (2) Wait at least four bus cycles before checking FCBEF or FCCF. YES ERROR EXIT NO YES NEW BURST COMMAND ? NO 0 FCCF ? 1 DONE Figure 4-3. Flash Burst Program Flowchart 4.5.
Chapter 4 Memory Map and Register Definition • • • • • • • • 4.5.6 Writing a second time to a flash address before launching the previous command (There is only one write to flash for every command.) Writing a second time to FCMD before launching the previous command (There is only one write to FCMD for every command.
Chapter 4 Memory Map and Register Definition One use for block protection is to block protect an area of flash memory for a bootloader program. This bootloader program then can be used to erase the rest of the flash memory and reprogram it. Because the bootloader is protected, it remains intact even if MCU power is lost in the middle of an erase and reprogram operation. 4.5.7 Vector Redirection Whenever any block protection is enabled, the reset and interrupt vectors will be protected.
Chapter 4 Memory Map and Register Definition is no way to disengage security without completely erasing all flash locations. If KEYEN is 1, a secure user program can temporarily disengage security by: 1. Writing 1 to KEYACC in the FCNFG register. This makes the flash module interpret writes to the backdoor comparison key locations (NVBACKKEY through NVBACKKEY+7) as values to be compared against the key rather than as the first step in a flash program or erase command. 2.
Chapter 4 Memory Map and Register Definition 7 R 6 5 4 3 2 1 0 0 0 0 DIVLD PRDIV8 DIV W Reset 0 0 0 0 0 = Unimplemented or Reserved Figure 4-5. Flash Clock Divider Register (FCDIV) Table 4-6. FCDIV Register Field Descriptions Field Description 7 DIVLD Divisor Loaded Status Flag — When set, this read-only status flag indicates that the FCDIV register has been written since reset.
Chapter 4 Memory Map and Register Definition 4.7.2 Flash Options Register (FOPT and NVOPT) During reset, the contents of the nonvolatile location NVOPT are copied from flash into FOPT. To change the value in this register, erase and reprogram the NVOPT location in flash memory as usual and then issue a new MCU reset. R 7 6 5 4 3 2 1 0 KEYEN FNORED 0 0 0 0 SEC01 SEC00 W Reset This register is loaded from nonvolatile location NVOPT during reset. = Unimplemented or Reserved Figure 4-6.
Chapter 4 Memory Map and Register Definition 4.7.3 R Flash Configuration Register (FCNFG) 7 6 0 0 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 KEYACC W Reset 0 0 0 = Unimplemented or Reserved Figure 4-7. Flash Configuration Register (FCNFG) Table 4-10. FCNFG Register Field Descriptions Field Description 5 KEYACC Enable Writing of Access Key — This bit enables writing of the backdoor comparison key. For more detailed information about the backdoor key mechanism, refer to Section 4.
Chapter 4 Memory Map and Register Definition 4.7.5 Flash Status Register (FSTAT) 7 R 6 5 4 FPVIOL FACCERR 0 0 FCCF FCBEF 3 2 1 0 0 FBLANK 0 0 0 0 0 0 W Reset 1 1 = Unimplemented or Reserved Figure 4-9. Flash Status Register (FSTAT) Table 4-12. FSTAT Register Field Descriptions Field Description 7 FCBEF Flash Command Buffer Empty Flag — The FCBEF bit is used to launch commands.
Chapter 4 Memory Map and Register Definition 4.7.6 Flash Command Register (FCMD) Only five command codes are recognized in normal user modes as shown in Table 4-13. Refer to Section 4.5.3, “Program and Erase Command Execution,” for a detailed discussion of flash programming and erase operations. R 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 W Reset FCMD 0 0 0 0 = Unimplemented or Reserved Figure 4-10. Flash Command Register (FCMD) Table 4-13.
Chapter 4 Memory Map and Register Definition MC9S08QD4 Series MCU Data Sheet, Rev.
Chapter 5 Resets, Interrupts, and General System Control 5.1 Introduction This chapter discusses basic reset and interrupt mechanisms and the various sources of reset and interrupts in the MC9S08QD4 series. Some interrupt sources from peripheral modules are discussed in greater detail within other sections of this data sheet. This section gathers basic information about all reset and interrupt sources in one place for easy reference.
Chapter 5 Resets, Interrupts, and General System Control 5.4 Computer Operating Properly (COP) Watchdog The COP watchdog is intended to force a system reset when the application software fails to execute as expected. To prevent a system reset from the COP timer (when it is enabled), application software must reset the COP counter periodically.
Chapter 5 Resets, Interrupts, and General System Control 5.5 Interrupts Interrupts provide a way to save the current CPU status and registers, execute an interrupt service routine (ISR), and then restore the CPU status so processing resumes where it was before the interrupt. Other than the software interrupt (SWI), which is a program instruction, interrupts are caused by hardware events such as an edge on the IRQ pin or a timer-overflow event.
Chapter 5 Resets, Interrupts, and General System Control 5.5.1 Interrupt Stack Frame Figure 5-1 shows the contents and organization of a stack frame. Before the interrupt, the stack pointer (SP) points at the next available byte location on the stack. The current values of CPU registers are stored on the stack starting with the low-order byte of the program counter (PCL) and ending with the CCR.
Chapter 5 Resets, Interrupts, and General System Control The IRQ pin when enabled defaults to use an internal pull device (IRQPDD = 0), the device is a pullup or pulldown depending on the polarity to detect. If the user desires to use an external pullup or pulldown, the IRQPDD can be written to a 1 to turn off the internal device. BIH and BIL instructions may be used to detect the level on the IRQ pin when the pin is configured to act as the IRQ input.
Chapter 5 Resets, Interrupts, and General System Control Table 5-2.
Chapter 5 Resets, Interrupts, and General System Control 5.6.1 Power-On Reset Operation When power is initially applied to the MCU, or when the supply voltage drops below the VPOR level, the POR circuit will cause a reset condition. As the supply voltage rises, the LVD circuit will hold the MCU in reset until the supply has risen above the VLVDL level. Both the POR bit and the LVD bit in SRS are set following a POR. 5.6.
Chapter 5 Resets, Interrupts, and General System Control 5.8 Reset, Interrupt, and System Control Registers and Control Bits One 8-bit register in the direct page register space and eight 8-bit registers in the high-page register space are related to reset and interrupt systems. Refer to the direct-page register summary in Chapter 3, “Modes of Operation,” for the absolute address assignments for all registers. This section refers to registers and control bits only by their names.
Chapter 5 Resets, Interrupts, and General System Control Table 5-3. IRQSC Register Field Descriptions (continued) Field Description 2 IRQACK IRQ Acknowledge — This write-only bit is used to acknowledge interrupt request events (write 1 to clear IRQF). Writing 0 has no meaning or effect. Reads always return 0. If edge-and-level detection is selected (IRQMOD = 1), IRQF cannot be cleared while the IRQ pin remains at its asserted level. 1 IRQIE 0 IRQMOD 5.8.
Chapter 5 Resets, Interrupts, and General System Control Table 5-4. SRS Register Field Descriptions (continued) Field Description 5 COP Computer Operating Properly (COP) Watchdog — Reset was caused by the COP watchdog timer timing out. This reset source can be blocked by COPE = 0. 0 Reset not caused by COP timeout. 1 Reset caused by COP timeout. 4 ILOP Illegal Opcode — Reset was caused by an attempt to execute an unimplemented or illegal opcode.
Chapter 5 Resets, Interrupts, and General System Control 5.8.4 System Options Register 1 (SOPT1) This high-page register is a write-once register so only the first write after reset is honored. It can be read at any time. Any subsequent attempt to write to SOPT1 (intentionally or unintentionally) is ignored to avoid accidental changes to these sensitive settings.
Chapter 5 Resets, Interrupts, and General System Control 5.8.5 System Options Register 2 (SOPT2) This high-page register contains bits to configure MCU-specific features on MC9S08QD4 series devices. 7 R COPCLKS1 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W Reset: 0 = Unimplemented or Reserved 1 This bit can be written only one time after reset. Additional writes are ignored. Figure 5-6. System Options Register 2 (SOPT2) Table 5-7.
Chapter 5 Resets, Interrupts, and General System Control R 7 6 5 4 3 2 1 0 ID7 ID6 ID5 ID4 ID3 ID2 ID1 ID0 0 0 0 0 1 0 0 1 W Reset: = Unimplemented or Reserved Figure 5-8. System Device Identification Register — Low (SDIDL) Table 5-9. SDIDL Register Field Descriptions Field 7:0 ID[7:0] 5.8.7 Description Part Identification Number — Each derivative in the HCS08 family has a unique identification number. The MC9S08QD4 series is hard coded to the value 0x011.
Chapter 5 Resets, Interrupts, and General System Control Table 5-11. Real-Time Interrupt Period RTIS2:RTIS1:RTIS0 Using Internal 1 kHz Clock Source1 2 Using 32 kHz ICS Clock Source Period = text3 0:0:0 Disable RTI Disable RTI 0:0:1 8 ms text × 256 0:1:0 32 ms text × 1024 0:1:1 64 ms text × 2048 1:0:0 128 ms text × 4096 1:0:1 256 ms text × 8192 1:1:0 512 ms text × 16384 1:1:1 1.024 s text × 32768 1 Values are shown in this column based on tRTI = 1 ms. See tRTI in the Section A.8.
Chapter 5 Resets, Interrupts, and General System Control Table 5-12. SPMSC1 Register Field Descriptions (continued) Field Description 5 LVDIE Low-Voltage Detect Interrupt Enable — This bit enables hardware interrupt requests for LVDF. 0 Hardware interrupt disabled (use polling). 1 Request a hardware interrupt when LVDF = 1. 4 LVDRE Low-Voltage Detect Reset Enable — This write-once bit enables LVDF events to generate a hardware reset (provided LVDE = 1). 0 LVDF does not generate hardware resets.
Chapter 5 Resets, Interrupts, and General System Control Table 5-13. SPMSC2 Register Field Descriptions Field 7 LVWF 6 LVWACK Description Low-Voltage Warning Flag — The LVWF bit indicates the low voltage warning status. 0 Low voltage warning not preset. 1 Low voltage warning is present or was present. Low-Voltage Warning Acknowledge — The LVWACK bit is the low-voltage warning acknowledge. Writing a 1 to LVWACK clears LVWF to a 0 if a low voltage warning is not present.
Chapter 6 Parallel Input/Output Control This section explains software controls related to parallel input/output (I/O) and pin control. The MC9S08QD4 series has one parallel I/O port which include a total of 4 I/O pins, one output-only pin, and one input-only pin. See Section Chapter 2, “External Signal Description,” for more information about pin assignments and external hardware considerations of these pins. All of these I/O pins are shared with on-chip peripheral functions as shown in Table 2-1.
Chapter 6 Parallel Input/Output Control PTxDDn D Output Enable Q PTxDn D Output Data Q 1 Port Read Data 0 Input Data Synchronizer BUSCLK Figure 6-1. Parallel I/O Block Diagram The data direction control bit (PTxDDn) determines whether the output buffer for the associated pin is enabled, and also controls the source for port data register reads. The input buffer for the associated pin is always enabled unless the pin is enabled as an analog function or is an output-only pin.
Chapter 6 Parallel Input/Output Control • In stop1 mode, all internal registers including parallel I/O control and data registers are powered off. Each of the pins assumes its default reset state (output buffer and internal pullup disabled). Upon exit from stop1, all pins must be re-configured the same as if the MCU had been reset. Stop2 mode is a partial power-down mode, whereby latches maintain the pin state as before the STOP instruction was executed.
Chapter 6 Parallel Input/Output Control Table 6-1. PTAD Register Field Descriptions Field Description 5:0 PTAD[5:0] Port A Data Register Bits — For port A pins that are inputs, reads return the logic level on the pin. For port A pins that are configured as outputs, reads return the last value written to this register. Writes are latched into all bits of this register. For port A pins that are configured as outputs, the logic level is driven out the corresponding MCU pin.
Chapter 6 Parallel Input/Output Control 6.4.2.1 Port A Internal Pullup Enable (PTAPE) An internal pullup device can be enabled for each port pin by setting the corresponding bit in the pullup enable register (PTAPEn). The pullup device is disabled if the pin is configured as an output by the parallel I/O control logic or any shared peripheral function regardless of the state of the corresponding pullup enable register bit. The pullup device is also disabled if the pin is controlled by an analog function.
Chapter 6 Parallel Input/Output Control 6.4.2.3 Port A Drive Strength Select (PTADS) An output pin can be selected to have high output drive strength by setting the corresponding bit in the drive strength select register (PTADSn). When high drive is selected a pin is capable of sourcing and sinking greater current. Even though every I/O pin can be selected as high drive, the user must ensure that the total current source and sink limits for the chip are not exceeded.
Chapter 7 Central Processor Unit (S08CPUV2) 7.1 Introduction This section provides summary information about the registers, addressing modes, and instruction set of the CPU of the HCS08 Family. For a more detailed discussion, refer to the HCS08 Family Reference Manual, volume 1, Freescale Semiconductor document order number HCS08RMV1/D. The HCS08 CPU is fully source- and object-code-compatible with the M68HC08 CPU.
Chapter 7 Central Processor Unit (S08CPUV2) 7.2 Programmer’s Model and CPU Registers Figure 7-1 shows the five CPU registers. CPU registers are not part of the memory map. 0 7 ACCUMULATOR A 16-BIT INDEX REGISTER H:X H INDEX REGISTER (HIGH) 8 15 INDEX REGISTER (LOW) 7 0 SP STACK POINTER 15 X 0 PROGRAM COUNTER 7 0 CONDITION CODE REGISTER V 1 1 H I N Z C PC CCR CARRY ZERO NEGATIVE INTERRUPT MASK HALF-CARRY (FROM BIT 3) TWO’S COMPLEMENT OVERFLOW Figure 7-1. CPU Registers 7.2.
Chapter 7 Central Processor Unit (S08CPUV2) 7.2.3 Stack Pointer (SP) This 16-bit address pointer register points at the next available location on the automatic last-in-first-out (LIFO) stack. The stack may be located anywhere in the 64-Kbyte address space that has RAM and can be any size up to the amount of available RAM. The stack is used to automatically save the return address for subroutine calls, the return address and CPU registers during interrupts, and for local variables.
Chapter 7 Central Processor Unit (S08CPUV2) 7 0 CONDITION CODE REGISTER V 1 1 H I N Z C CCR CARRY ZERO NEGATIVE INTERRUPT MASK HALF-CARRY (FROM BIT 3) TWO’S COMPLEMENT OVERFLOW Figure 7-2. Condition Code Register Table 7-1. CCR Register Field Descriptions Field Description 7 V Two’s Complement Overflow Flag — The CPU sets the overflow flag when a two’s complement overflow occurs. The signed branch instructions BGT, BGE, BLE, and BLT use the overflow flag.
Chapter 7 Central Processor Unit (S08CPUV2) 7.3 Addressing Modes Addressing modes define the way the CPU accesses operands and data. In the HCS08, all memory, status and control registers, and input/output (I/O) ports share a single 64-Kbyte linear address space so a 16-bit binary address can uniquely identify any memory location. This arrangement means that the same instructions that access variables in RAM can also be used to access I/O and control registers or nonvolatile program space.
Chapter 7 Central Processor Unit (S08CPUV2) 7.3.5 Extended Addressing Mode (EXT) In extended addressing mode, the full 16-bit address of the operand is located in the next two bytes of program memory after the opcode (high byte first). 7.3.6 Indexed Addressing Mode Indexed addressing mode has seven variations including five that use the 16-bit H:X index register pair and two that use the stack pointer as the base reference. 7.3.6.
Chapter 7 Central Processor Unit (S08CPUV2) 7.3.6.7 SP-Relative, 16-Bit Offset (SP2) This variation of indexed addressing uses the 16-bit value in the stack pointer (SP) plus a 16-bit offset included in the instruction as the address of the operand needed to complete the instruction. 7.4 Special Operations The CPU performs a few special operations that are similar to instructions but do not have opcodes like other CPU instructions.
Chapter 7 Central Processor Unit (S08CPUV2) interrupt service routine, this would allow nesting of interrupts (which is not recommended because it leads to programs that are difficult to debug and maintain). For compatibility with the earlier M68HC05 MCUs, the high-order half of the H:X index register pair (H) is not saved on the stack as part of the interrupt sequence.
Chapter 7 Central Processor Unit (S08CPUV2) 7.4.5 BGND Instruction The BGND instruction is new to the HCS08 compared to the M68HC08. BGND would not be used in normal user programs because it forces the CPU to stop processing user instructions and enter the active background mode. The only way to resume execution of the user program is through reset or by a host debug system issuing a GO, TRACE1, or TAGGO serial command through the background debug interface.
Chapter 7 Central Processor Unit (S08CPUV2) 7.5 HCS08 Instruction Set Summary Table 7-2 provides a summary of the HCS08 instruction set in all possible addressing modes. The table shows operand construction, execution time in internal bus clock cycles, and cycle-by-cycle details for each addressing mode variation of each instruction. Table 7-2.
Chapter 7 Central Processor Unit (S08CPUV2) Table 7-2.
Chapter 7 Central Processor Unit (S08CPUV2) Table 7-2.
Chapter 7 Central Processor Unit (S08CPUV2) Table 7-2.
Chapter 7 Central Processor Unit (S08CPUV2) Table 7-2.
Chapter 7 Central Processor Unit (S08CPUV2) Table 7-2.
Chapter 7 Central Processor Unit (S08CPUV2) Table 7-2.
Chapter 7 Central Processor Unit (S08CPUV2) Table 7-2.
Chapter 7 Central Processor Unit (S08CPUV2) Table 7-2. Instruction Set Summary (Sheet 9 of 9) Object Code Cycles Operation Address Mode Source Form Cyc-by-Cyc Details Affect on CCR VH I N Z C TXS Transfer Index Reg. to SP SP ← (H:X) – $0001 INH 94 2 fp –– – – – – WAIT Enable Interrupts; Wait for Interrupt I bit ← 0; Halt CPU INH 8F 2+ fp...
Chapter 7 Central Processor Unit (S08CPUV2) Table 7-3.
Chapter 7 Central Processor Unit (S08CPUV2) Table 7-3.
Chapter 8 Analog-to-Digital Converter (ADC10V1) 8.1 Introduction The 10-bit analog-to-digital converter (ADC) is a successive approximation ADC designed for operation within an integrated microcontroller system-on-chip. The ADC module design supports up to 28 separate analog inputs (AD0–AD27). Only four (ADC1P0–ADC1P3) of the possible inputs are implemented on the MC9S08QD4 series MCU. These inputs are selected by the ADCH bits. MC9S08QD4 Series MCU Data Sheet, Rev.
Chapter 8 Analog-to-Digital Converter (ADC10V1) BKGD/MS IRQ HCS08 CORE BDC HCS08 SYSTEM CONTROL RESETS AND INTERRUPTS MODES OF OPERATION POWER MANAGEMENT RTI COP IRQ LVD 4-BIT KEYBOARD INTERRUPT MODULE (KBI) 1-CH 16-BIT TIMER/PWM MODULE (TPM2) 2-CH 16-BIT TIMER/PWM MODULE (TPM1) USER FLASH 4096 / 2048 BYTES 10-BIT ANALOG-TO-DIGITAL CONVERTER (ADC) 4 TPM2CH0 TCLK2 TPM1CH0 TPM1CH1 TCLK1 PORT A CPU PTA5/TPM2CH0I/IRQ/RESET PTA4/TPM2CH0O/BKGD/MS PTA3/KBI1P3/TCLK2/ADC1P3 PTA2/KBI1P2/TCLK1/ADC1P2 PTA1
Chapter 8 Analog-to-Digital Converter (ADC10V1) 8.1.1.1 Channel Assignments The ADC channel assignments for the MC9S08QD4 series devices are shown in Table 8-1. Reserved channels convert to an unknown value. Table 8-1.
Chapter 8 Analog-to-Digital Converter (ADC10V1) The RTI can be configured to cause a hardware trigger in MCU run, wait, and stop3. 8.1.1.4 Analog Pin Enables The ADC on MC9S08QD4 contains only one analog pin enable register, APCTL1. 8.1.1.
Analog-to-Digital Converter (S08ADC10V1) 8.1.2 Features Features of the ADC module include: • Linear successive approximation algorithm with 10 bits resolution. • Up to 28 analog inputs. • Output formatted in 10- or 8-bit right-justified format. • Single or continuous conversion (automatic return to idle after single conversion). • Configurable sample time and conversion speed/power. • Conversion complete flag and interrupt. • Input clock selectable from up to four sources.
Analog-to-Digital Converter (S08ADC10V1) ADIV ADLPC MODE ADLSMP ADTRG 2 ADCO ADCH 1 ADCCFG complete COCO ADCSC1 ADICLK Compare true AIEN 3 Async Clock Gen ADACK MCU STOP ADCK ÷2 ALTCLK abort transfer sample initialize ••• AD0 convert Control Sequencer ADHWT Bus Clock Clock Divide AIEN 1 COCO 2 ADVIN Interrupt SAR Converter AD27 VREFH Data Registers Sum VREFL Compare true 3 Compare Value Registers ACFGT Value Compare Logic ADCSC2 Figure 8-2.
Analog-to-Digital Converter (S08ADC10V1) 8.2.1 Analog Power (VDDAD) The ADC analog portion uses VDDAD as its power connection. In some packages, VDDAD is connected internally to VDD. If externally available, connect the VDDAD pin to the same voltage potential as VDD. External filtering may be necessary to ensure clean VDDAD for good results. 8.2.2 Analog Ground (VSSAD) The ADC analog portion uses VSSAD as its ground connection. In some packages, VSSAD is connected internally to VSS.
Analog-to-Digital Converter (S08ADC10V1) 7 R 6 5 4 AIEN ADCO 0 0 3 2 1 0 1 1 COCO ADCH W Reset: 0 1 1 1 = Unimplemented or Reserved Figure 8-3. Status and Control Register (ADCSC1) Table 8-3. ADCSC1 Register Field Descriptions Field Description 7 COCO Conversion Complete Flag — The COCO flag is a read-only bit which is set each time a conversion is completed when the compare function is disabled (ACFE = 0).
Analog-to-Digital Converter (S08ADC10V1) Figure 8-4. Input Channel Select (continued) 8.3.
Analog-to-Digital Converter (S08ADC10V1) Table 8-4. ADCSC2 Register Field Descriptions (continued) Field Description 5 ACFE Compare Function Enable — ACFE is used to enable the compare function. 0 Compare function disabled 1 Compare function enabled 4 ACFGT Compare Function Greater Than Enable — ACFGT is used to configure the compare function to trigger when the result of the conversion of the input being monitored is greater than or equal to the compare value.
Analog-to-Digital Converter (S08ADC10V1) R 7 6 5 4 3 2 1 0 ADR7 ADR6 ADR5 ADR4 ADR3 ADR2 ADR1 ADR0 0 0 0 0 0 0 0 0 W Reset: = Unimplemented or Reserved Figure 8-7. Data Result Low Register (ADCRL) 8.3.5 Compare Value High Register (ADCCVH) This register holds the upper two bits of the 10-bit compare value. These bits are compared to the upper two bits of the result following a conversion in 10-bit mode when the compare function is enabled.
Analog-to-Digital Converter (S08ADC10V1) 7 6 5 4 3 2 1 0 R ADLPC ADIV ADLSMP MODE ADICLK W Reset: 0 0 0 0 0 0 0 0 Figure 8-10. Configuration Register (ADCCFG) Table 8-5. ADCCFG Register Field Descriptions Field Description 7 ADLPC Low Power Configuration — ADLPC controls the speed and power configuration of the successive approximation converter. This is used to optimize power consumption when higher sample rates are not required.
Analog-to-Digital Converter (S08ADC10V1) Table 8-8. Input Clock Select ADICLK Selected Clock Source 00 8.3.8 Bus clock 01 Bus clock divided by 2 10 Alternate clock (ALTCLK) 11 Asynchronous clock (ADACK) Pin Control 1 Register (APCTL1) The pin control registers are used to disable the I/O port control of MCU pins used as analog inputs. APCTL1 is used to control the pins associated with channels 0–7 of the ADC module.
Analog-to-Digital Converter (S08ADC10V1) Table 8-9. APCTL1 Register Field Descriptions (continued) Field Description 1 ADPC1 ADC Pin Control 1 — ADPC1 is used to control the pin associated with channel AD1. 0 AD1 pin I/O control enabled 1 AD1 pin I/O control disabled 0 ADPC0 ADC Pin Control 0 — ADPC0 is used to control the pin associated with channel AD0. 0 AD0 pin I/O control enabled 1 AD0 pin I/O control disabled 8.3.
Analog-to-Digital Converter (S08ADC10V1) Table 8-10. APCTL2 Register Field Descriptions (continued) Field Description 1 ADPC9 ADC Pin Control 9 — ADPC9 is used to control the pin associated with channel AD9. 0 AD9 pin I/O control enabled 1 AD9 pin I/O control disabled 0 ADPC8 ADC Pin Control 8 — ADPC8 is used to control the pin associated with channel AD8. 0 AD8 pin I/O control enabled 1 AD8 pin I/O control disabled 8.3.
Analog-to-Digital Converter (S08ADC10V1) Table 8-11. APCTL3 Register Field Descriptions (continued) Field Description 1 ADPC17 ADC Pin Control 17 — ADPC17 is used to control the pin associated with channel AD17. 0 AD17 pin I/O control enabled 1 AD17 pin I/O control disabled 0 ADPC16 ADC Pin Control 16 — ADPC16 is used to control the pin associated with channel AD16. 0 AD16 pin I/O control enabled 1 AD16 pin I/O control disabled 8.
Analog-to-Digital Converter (S08ADC10V1) are too fast, then the clock must be divided to the appropriate frequency. This divider is specified by the ADIV bits and can be divide-by 1, 2, 4, or 8. 8.4.2 Input Select and Pin Control The pin control registers (APCTL3, APCTL2, and APCTL1) are used to disable the I/O port control of the pins used as analog inputs.
Analog-to-Digital Converter (S08ADC10V1) 8.4.4.2 Completing Conversions A conversion is completed when the result of the conversion is transferred into the data result registers, ADCRH and ADCRL. This is indicated by the setting of COCO. An interrupt is generated if AIEN is high at the time that COCO is set.
Analog-to-Digital Converter (S08ADC10V1) result of the conversion is transferred to ADCRH and ADCRL upon completion of the conversion algorithm. If the bus frequency is less than the fADCK frequency, precise sample time for continuous conversions cannot be guaranteed when short sample is enabled (ADLSMP=0). If the bus frequency is less than 1/11th of the fADCK frequency, precise sample time for continuous conversions cannot be guaranteed when long sample is enabled (ADLSMP=1).
Analog-to-Digital Converter (S08ADC10V1) 8.4.5 Automatic Compare Function The compare function can be configured to check for either an upper limit or lower limit. After the input is sampled and converted, the result is added to the two’s complement of the compare value (ADCCVH and ADCCVL). When comparing to an upper limit (ACFGT = 1), if the result is greater-than or equal-to the compare value, COCO is set.
Analog-to-Digital Converter (S08ADC10V1) 8.4.7.2 Stop3 Mode With ADACK Enabled If ADACK is selected as the conversion clock, the ADC continues operation during stop3 mode. For guaranteed ADC operation, the MCU’s voltage regulator must remain active during stop3 mode. Consult the module introduction for configuration information for this MCU. If a conversion is in progress when the MCU enters stop3 mode, it continues until completion.
Analog-to-Digital Converter (S08ADC10V1) 2. Update status and control register 2 (ADCSC2) to select the conversion trigger (hardware or software) and compare function options, if enabled. 3. Update status and control register 1 (ADCSC1) to select whether conversions will be continuous or completed only once, and to enable or disable conversion complete interrupts. The input channel on which conversions will be performed is also selected here. 8.5.1.
Analog-to-Digital Converter (S08ADC10V1) RESET INITIALIZE ADC ADCCFG = $98 ADCSC2 = $00 ADCSC1 = $41 CHECK COCO=1? NO YES READ ADCRH THEN ADCRL TO CLEAR COCO BIT CONTINUE Figure 8-14. Initialization Flowchart for Example 8.6 Application Information This section contains information for using the ADC module in applications. The ADC has been designed to be integrated into a microcontroller for use in embedded control applications requiring an A/D converter. 8.6.
Analog-to-Digital Converter (S08ADC10V1) In cases where separate power supplies are used for analog and digital power, the ground connection between these supplies must be at the VSSAD pin. This must be the only ground connection between these supplies if possible. The VSSAD pin makes a good single point ground location. 8.6.1.2 Analog Reference Pins In addition to the analog supplies, the ADC module has connections for two reference voltage inputs.
Analog-to-Digital Converter (S08ADC10V1) 8.6.2 Sources of Error Several sources of error exist for A/D conversions. These are discussed in the following sections. 8.6.2.1 Sampling Error For proper conversions, the input must be sampled long enough to achieve the proper accuracy. Given the maximum input resistance of approximately 7kΩ and input capacitance of approximately 5.5 pF, sampling to within 1/4LSB (at 10-bit resolution) can be achieved within the minimum sample window (3.
Analog-to-Digital Converter (S08ADC10V1) • • Average the result by converting the analog input many times in succession and dividing the sum of the results. Four samples are required to eliminate the effect of a 1LSB, one-time error. Reduce the effect of synchronous noise by operating off the asynchronous clock (ADACK) and averaging. Noise that is synchronous to ADCK cannot be averaged out. 8.6.2.
Analog-to-Digital Converter (S08ADC10V1) converter yields the lower code (and vice-versa). However, even very small amounts of system noise can cause the converter to be indeterminate (between two codes) for a range of input voltages around the transition voltage. This range is normally around ±1/2 LSB and will increase with noise. This error may be reduced by repeatedly sampling the input and averaging the result. Additionally the techniques discussed in Section 8.6.2.
Analog-to-Digital Converter (S08ADC10V1) MC9S08QD4 Series MCU Data Sheet, Rev.
Chapter 9 Internal Clock Source (S08ICSV1) 9.1 Introduction The internal clock source (ICS) module provides clock source choices for the MCU. The module contains a frequency-locked loop (FLL) as a clock source that is controllable by an internal reference clock. The module can provide this FLL clock or the internal reference clock as a source for the MCU system clock, ICSOUT.
Chapter 9 Internal Clock Source (S08ICSV1) BKGD/MS IRQ HCS08 CORE BDC HCS08 SYSTEM CONTROL RESETS AND INTERRUPTS MODES OF OPERATION POWER MANAGEMENT RTI COP IRQ LVD USER FLASH 4096 / 2048 BYTES 4-BIT KEYBOARD INTERRUPT MODULE (KBI) 1-CH 16-BIT TIMER/PWM MODULE (TPM2) 2-CH 16-BIT TIMER/PWM MODULE (TPM1) 10-BIT ANALOG-TO-DIGITAL CONVERTER (ADC) 4 TPM2CH0 TCLK2 TPM1CH0 TPM1CH1 TCLK1 PORT A CPU PTA5/TPM2CH0I/IRQ/RESET PTA4/TPM2CH0O/BKGD/MS PTA3/KBI1P3/TCLK2/ADC1P3 PTA2/KBI1P2/TCLK1/ADC1P2 PTA1/KBI1
Internal Clock Source (S08ICSV1) 9.1.2 Features Key features of the ICS module are: • Frequency-locked loop (FLL) is trimmable for accuracy — 0.
Internal Clock Source (S08ICSV1) 9.1.3.5 FLL Bypassed External (FBE) In FLL bypassed external mode, the FLL is enabled and controlled by an external reference clock, but is bypassed. The ICS supplies a clock derived from the external reference clock. The external reference clock can be an external crystal/resonator supplied by an OSC controlled by the ICS, or it can be another external clock source. The BDC clock is supplied from the FLL. 9.1.3.
Internal Clock Source (S08ICSV1) 9.2 External Signal Description There are no ICS signals that connect off chip. 9.3 Register Definition 9.3.1 ICS Control Register 1 (ICSC1) 7 6 5 4 3 2 1 0 IREFS IRCLKEN IREFSTEN 1 0 0 R CLKS RDIV W Reset: 0 0 0 0 0 Figure 9-3. ICS Control Register 1 (ICSC1) Table 9-1. ICS Control Register 1 Field Descriptions Field Description 7:6 CLKS Clock Source Select — Selects the clock source that controls the bus frequency.
Internal Clock Source (S08ICSV1) 9.3.2 ICS Control Register 2 (ICSC2) 7 6 5 4 3 2 RANGE HGO LP EREFS 0 0 0 0 1 0 R BDIV ERCLKEN EREFSTEN W Reset: 0 1 0 0 Figure 9-4. ICS Control Register 2 (ICSC2) Table 9-2. ICS Control Register 2 Field Descriptions Field Description 7:6 BDIV Bus Frequency Divider — Selects the amount to divide down the clock source selected by the CLKS bits. This controls the bus frequency.
Internal Clock Source (S08ICSV1) 9.3.3 ICS Trim Register (ICSTRM) 7 6 5 4 3 2 1 0 R TRIM W POR: 1 0 0 0 0 0 0 0 Reset: U U U U U U U U Figure 9-5. ICS Trim Register (ICSTRM) Table 9-3. ICS Trim Register Field Descriptions Field Description 7:0 TRIM ICS Trim Setting — The TRIM bits control the internal reference clock frequency by controlling the internal reference clock period. The bits’ effect are binary weighted (i.e., bit 1 will adjust twice as much as bit 0).
Internal Clock Source (S08ICSV1) 9.4 Functional Description 9.4.
Internal Clock Source (S08ICSV1) 9.4.1.2 FLL Engaged External (FEE) The FLL engaged external (FEE) mode is entered when all the following conditions occur: • • • CLKS bits are written to 00 IREFS bit is written to 0 RDIV bits are written to divide reference clock to be within the range of 31.25 kHz to 39.0625 kHz In FLL engaged external mode, the ICSOUT clock is derived from the FLL clock which is controlled by the external reference clock.
Internal Clock Source (S08ICSV1) times the filter frequency, as selected by the RDIV bits, so that the ICSLCLK will be available for BDC communications, and the external reference clock is enabled. 9.4.1.6 FLL Bypassed External Low Power (FBELP) The FLL bypassed external low power (FBELP) mode is entered when all the following conditions occur: • CLKS bits are written to 10. • IREFS bit is written to 0. • BDM mode is not active and LP bit is written to 1.
Internal Clock Source (S08ICSV1) 9.4.4 Low Power Bit Usage The low power bit (LP) is provided to allow the FLL to be disabled and thus conserve power when it is not being used. However, in some applications it may be desirable to enable the FLL and allow it to lock for maximum accuracy before switching to an FLL engaged mode. Do this by writing the LP bit to 0. 9.4.
Internal Clock Source (S08ICSV1) 9.4.7 Fixed Frequency Clock The ICS presents the divided FLL reference clock as ICSFFCLK for use as an additional clock source for peripheral modules. The ICS provides an output signal (ICSFFE) which indicates when the ICS is providing ICSOUT frequencies four times or greater than the divided FLL reference clock (ICSFFCLK). In FLL engaged mode (FEI and FEE) this is always true and ICSFFE is always high.
Internal Clock Source (S08ICSV1) — If entering FEE, set the reference divider and clear the IREFS bit to switch to the external reference. — The internal reference can optionally be kept running by setting the IRCLKEN bit. This is useful if the application will switch back and forth between internal clock and external clock modes. For minimum power consumption, leave the internal reference disabled while in an external clock mode. 4.
Internal Clock Source (S08ICSV1) MC9S08QD4 Series MCU Data Sheet, Rev.
Chapter 10 Keyboard Interrupt (S08KBIV2) 10.1 Introduction The keyboard interrupt KBI module provides up to eight independently enabled external interrupt sources. Only four (KBI1P0–KBI1P3) of the possible interrupts are implemented on the MC9S08QD4 series MCU. These inputs are selected by the KBIPE bits. Figure 10-1 Shows the MC9S08QD4 series with the KBI module and pins highlighted. MC9S08QD4 Series MCU Data Sheet, Rev.
Chapter 10 Keyboard Interrupt (S08KBIV2) BKGD/MS IRQ HCS08 CORE BDC HCS08 SYSTEM CONTROL RESETS AND INTERRUPTS MODES OF OPERATION POWER MANAGEMENT RTI COP IRQ LVD USER FLASH 4096 / 2048 BYTES 4-BIT KEYBOARD INTERRUPT MODULE (KBI) 1-CH 16-BIT TIMER/PWM MODULE (TPM2) 2-CH 16-BIT TIMER/PWM MODULE (TPM1) 10-BIT ANALOG-TO-DIGITAL CONVERTER (ADC) 4 TPM2CH0 TCLK2 TPM1CH0 TPM1CH1 TCLK1 PORT A CPU PTA5/TPM2CH0I/IRQ/RESET PTA4/TPM2CH0O/BKGD/MS PTA3/KBI1P3/TCLK2/ADC1P3 PTA2/KBI1P2/TCLK1/ADC1P2 PTA1/KBI1P1
Keyboard Interrupts (S08KBIV2) 10.1.1 Features The KBI features include: • Up to eight keyboard interrupt pins with individual pin enable bits. • Each keyboard interrupt pin is programmable as falling edge (or rising edge) only, or both falling edge and low level (or both rising edge and high level) interrupt sensitivity. • One software enabled keyboard interrupt. • Exit from low-power modes. 10.1.2 Modes of Operation This section defines the KBI operation in wait, stop, and background debug modes.
Keyboard Interrupts (S08KBIV2) BUSCLK KBACK VDD 1 KBIP0 0 S RESET KBF D CLR Q KBIPE0 SYNCHRONIZER CK KBEDG0 KEYBOARD INTERRUPT FF 1 KBIPn 0 S STOP STOP BYPASS KBI INTERRU PT KBMOD KBIPEn KBIE KBEDGn Figure 10-2. KBI Block Diagram 10.2 External Signal Description The KBI input pins can be used to detect either falling edges, or both falling edge and low level interrupt requests.
Keyboard Interrupts (S08KBIV2) R 7 6 5 4 3 2 0 0 0 0 KBF 0 W Reset: 1 0 KBIE KBMOD 0 0 KBACK 0 0 0 0 0 0 = Unimplemented Figure 10-3. KBI Status and Control Register Table 10-2. KBISC Register Field Descriptions Field Description 7:4 Unused register bits, always read 0. 3 KBF Keyboard Interrupt Flag — KBF indicates when a keyboard interrupt is detected. Writes have no effect on KBF. 0 No keyboard interrupt detected. 1 Keyboard interrupt detected.
Keyboard Interrupts (S08KBIV2) 7 6 5 4 3 2 1 0 KBEDG7 KBEDG6 KBEDG5 KBEDG4 KBEDG3 KBEDG2 KBEDG1 KBEDG0 0 0 0 0 0 0 0 0 R W Reset: Figure 10-5. KBI Edge Select Register Table 10-4. KBIES Register Field Descriptions Field 7:0 KBEDGn 10.4 Description Keyboard Edge Selects — Each of the KBEDGn bits selects the falling edge/low level or rising edge/high level function of the corresponding pin). 0 Falling edge/low level. 1 Rising edge/high level.
Keyboard Interrupts (S08KBIV2) KBISC provided all enabled keyboard inputs are at their deasserted levels. KBF will remain set if any enabled KBI pin is asserted while attempting to clear by writing a 1 to KBACK. 10.4.3 KBI Pullup/Pulldown Resistors The KBI pins can be configured to use an internal pullup/pulldown resistor using the associated I/O port pullup enable register.
Keyboard Interrupts (S08KBIV2) MC9S08QD4 Series MCU Data Sheet, Rev.
Chapter 11 Timer/Pulse-Width Modulator (S08TPMV2) 11.1 Introduction Figure 11-1 shows the MC9S08QD4 series block diagram with the TPM module and pins highlighted. 11.1.1 TPM2 Configuration Information The TPM2 module consist of a single channel, TPM2CH0, that is multiplexed with input pin PTA4 and output pin PTA5. When TPM2 is configured for input capture, the TPM2CH0 will connect to the PTA5 (TPM2CH0I). When TPM2 is configured for output compare, the TPM2CH0 will connect to the PTA4 (TPM2CH0O).
Chapter 11 Timer/Pulse-Width Modulator (S08TPMV2) BKGD/MS IRQ HCS08 CORE BDC HCS08 SYSTEM CONTROL RESETS AND INTERRUPTS MODES OF OPERATION POWER MANAGEMENT RTI COP IRQ LVD USER FLASH 4096 / 2048 BYTES 4-BIT KEYBOARD INTERRUPT MODULE (KBI) 1-CH 16-BIT TIMER/PWM MODULE (TPM2) 2-CH 16-BIT TIMER/PWM MODULE (TPM1) 10-BIT ANALOG-TO-DIGITAL CONVERTER (ADC) 4 TPM2CH0 TCLK2 TPM1CH0 TPM1CH1 TCLK1 PORT A CPU PTA5/TPM2CH0I/IRQ/RESET PTA4/TPM2CH0O/BKGD/MS PTA3/KBI1P3/TCLK2/ADC1P3 PTA2/KBI1P2/TCLK1/ADC1P2 PT
Timer/Pulse-Width Modulator (S08TPMV2) 11.1.
Timer/Pulse-Width Modulator (S08TPMV2) BUSCLK XCLK TPMxCLK SYNC CLOCK SOURCE SELECT OFF, BUS, XCLK, EXT CLKSB PRESCALE AND SELECT DIVIDE BY 1, 2, 4, 8, 16, 32, 64, or 128 PS2 CLKSA PS1 PS0 CPWMS MAIN 16-BIT COUNTER TOF COUNTER RESET INTERRUPT LOGIC TOIE 16-BIT COMPARATOR TPMxMODH:TPMxMO CHANNEL 0 ELS0B ELS0A PORT LOGIC 16-BIT COMPARATOR TPMxC0VH:TPMxC0VL CH0F INTERRUPT LOGIC MS0B MS0A ELS1B ELS1A CH0IE TPMxC1VH:TPMxC1VL CH1F INTERRUPT LOGIC 16-BIT LATCH MS1A ELSnB ELSnA TPMxCH
Timer/Pulse-Width Modulator (S08TPMV2) All TPM channels are programmable independently as input capture, output compare, or buffered edge-aligned PWM channels. 11.2 External Signal Description When any pin associated with the timer is configured as a timer input, a passive pullup can be enabled. After reset, the TPM modules are disabled and all pins default to general-purpose inputs with the passive pullups disabled. 11.2.
Timer/Pulse-Width Modulator (S08TPMV2) Freescale-provided equate or header file is used to translate these names into the appropriate absolute addresses. 11.3.1 Timer Status and Control Register (TPMxSC) TPMxSC contains the overflow status flag and control bits that are used to configure the interrupt enable, TPM configuration, clock source, and prescale divisor. These controls relate to all channels within this timer module.
Timer/Pulse-Width Modulator (S08TPMV2) Table 11-2. TPM Clock Source Selection CLKSB:CLKSA TPM Clock Source to Prescaler Input 0:0 No clock selected (TPMx disabled) 0:1 Bus rate clock (BUSCLK) 1:0 Fixed system clock (XCLK) 1:1 External source (TPMxCLK)1,2 1 The maximum frequency that is allowed as an external clock is one-fourth of the bus frequency.
Timer/Pulse-Width Modulator (S08TPMV2) R 7 6 5 4 3 2 1 0 Bit 7 6 5 4 3 2 1 Bit 0 0 0 W Reset Any write to TPMxCNTL clears the 16-bit counter. 0 0 0 0 0 0 Figure 11-5. Timer Counter Register Low (TPMxCNTL) When background mode is active, the timer counter and the coherency mechanism are frozen such that the buffer latches remain in the state they were in when the background mode became active even if one or both bytes of the counter are read while background mode is active. 11.3.
Timer/Pulse-Width Modulator (S08TPMV2) 11.3.4 Timer Channel n Status and Control Register (TPMxCnSC) TPMxCnSC contains the channel interrupt status flag and control bits that are used to configure the interrupt enable, channel configuration, and pin function. 7 6 5 4 3 2 CHnF CHnIE MSnB MSnA ELSnB ELSnA 0 0 0 0 0 0 R 1 0 0 0 0 0 W Reset = Unimplemented or Reserved Figure 11-8. Timer Channel n Status and Control Register (TPMxCnSC) Table 11-4.
Timer/Pulse-Width Modulator (S08TPMV2) Table 11-5.
Timer/Pulse-Width Modulator (S08TPMV2) In output compare or PWM modes, writing to either byte (TPMxCnVH or TPMxCnVL) latches the value into a buffer. When both bytes have been written, they are transferred as a coherent 16-bit value into the timer channel value registers. This latching mechanism may be manually reset by writing to the TPMxCnSC register. This latching mechanism allows coherent 16-bit writes in either order, which is friendly to various compiler implementations. 11.
Timer/Pulse-Width Modulator (S08TPMV2) When center-aligned PWM operation is specified, the counter counts upward from 0x0000 through its terminal count and then counts downward to 0x0000 where it returns to up-counting. Both 0x0000 and the terminal count value (value in TPMxMODH:TPMxMODL) are normal length counts (one timer clock period long). An interrupt flag and enable are associated with the main 16-bit counter.
Timer/Pulse-Width Modulator (S08TPMV2) 11.4.2.2 Output Compare Mode With the output compare function, the TPM can generate timed pulses with programmable position, polarity, duration, and frequency. When the counter reaches the value in the channel value registers of an output compare channel, the TPM can set, clear, or toggle the channel pin.
Timer/Pulse-Width Modulator (S08TPMV2) 11.4.3 Center-Aligned PWM Mode This type of PWM output uses the up-/down-counting mode of the timer counter (CPWMS = 1). The output compare value in TPMxCnVH:TPMxCnVL determines the pulse width (duty cycle) of the PWM signal and the period is determined by the value in TPMxMODH:TPMxMODL. TPMxMODH:TPMxMODL must be kept in the range of 0x0001 to 0x7FFF because values outside this range can produce ambiguous results.
Timer/Pulse-Width Modulator (S08TPMV2) transferred to the corresponding timer channel registers only after both 8-bit bytes of a 16-bit register have been written and the timer counter overflows (reverses direction from up-counting to down-counting at the end of the terminal count in the modulus register). This TPMxCNT overflow requirement only applies to PWM channels, not output compares. Optionally, when TPMxCNTH:TPMxCNTL = TPMxMODH:TPMxMODL, the TPM can generate a TOF interrupt at the end of this count.
Timer/Pulse-Width Modulator (S08TPMV2) 11.5.3 Channel Event Interrupt Description The meaning of channel interrupts depends on the current mode of the channel (input capture, output compare, edge-aligned PWM, or center-aligned PWM). When a channel is configured as an input capture channel, the ELSnB:ELSnA control bits select rising edges, falling edges, any edge, or no edge (off) as the edge that triggers an input capture event. When the selected edge is detected, the interrupt flag is set.
Chapter 12 Development Support 12.1 Introduction Development support systems in the HCS08 include the background debug controller (BDC). The BDC provides a single-wire debug interface to the target MCU that provides a convenient interface for programming the on-chip flash and other nonvolatile memories.
Development Support 12.1.
Development Support BKGD 1 2 GND NO CONNECT 3 4 RESET NO CONNECT 5 6 VDD Figure 12-1. BDM Tool Connector 12.2.1 BKGD Pin Description BKGD is the single-wire background debug interface pin. The primary function of this pin is for bidirectional serial communication of active background mode commands and data. During reset, this pin is used to select between starting in active background mode or starting the user’s application program.
Development Support when this timeout occurs is aborted without affecting the memory or operating mode of the target MCU system. The custom serial protocol requires the debug pod to know the target BDC communication clock speed. The clock switch (CLKSW) control bit in the BDC status and control register allows the user to select the BDC clock source. The BDC clock source can either be the bus or the alternate BDC clock source. The BKGD pin can receive a high or low level or transmit a high or low level.
Development Support BDC CLOCK (TARGET MCU) HOST DRIVE TO BKGD PIN TARGET MCU SPEEDUP PULSE HIGH-IMPEDANCE HIGH-IMPEDANCE HIGH-IMPEDANCE PERCEIVED START OF BIT TIME R-C RISE BKGD PIN 10 CYCLES 10 CYCLES EARLIEST START OF NEXT BIT HOST SAMPLES BKGD PIN Figure 12-3. BDC Target-to-Host Serial Bit Timing (Logic 1) Figure 12-4 shows the host receiving a logic 0 from the target HCS08 MCU.
Development Support BDC CLOCK (TARGET MCU) HOST DRIVE TO BKGD PIN HIGH-IMPEDANCE SPEEDUP PULSE TARGET MCU DRIVE AND SPEED-UP PULSE PERCEIVED START OF BIT TIME BKGD PIN 10 CYCLES 10 CYCLES EARLIEST START OF NEXT BIT HOST SAMPLES BKGD PIN Figure 12-4. BDM Target-to-Host Serial Bit Timing (Logic 0) 12.2.3 BDC Commands BDC commands are sent serially from a host computer to the BKGD pin of the target HCS08 MCU. All commands and data are sent MSB-first using a custom BDC communications protocol.
Development Support / d AAAA RD WD RD16 WD16 SS CC RBKP = = = = = = = = = = WBKP = Commands begin with an 8-bit hexadecimal command code in the host-to-target direction (most significant bit first) separates parts of the command delay 16 target BDC clock cycles a 16-bit address in the host-to-target direction 8 bits of read data in the target-to-host direction 8 bits of write data in the host-to-target direction 16 bits of read data in the target-to-host direction 16 bits of write data in the host-to-t
Development Support Table 12-1. BDC Command Summary Command Mnemonic 1 Active BDM/ Non-intrusive Coding Structure Description SYNC Non-intrusive n/a1 Request a timed reference pulse to determine target BDC communication speed ACK_ENABLE Non-intrusive D5/d Enable acknowledge protocol. Refer to Freescale document order no. HCS08RMv1/D. ACK_DISABLE Non-intrusive D6/d Disable acknowledge protocol. Refer to Freescale document order no. HCS08RMv1/D.
Development Support The SYNC command is unlike other BDC commands because the host does not necessarily know the correct communications speed to use for BDC communications until after it has analyzed the response to the SYNC command. To issue a SYNC command, the host: • Drives the BKGD pin low for at least 128 cycles of the slowest possible BDC clock (The slowest clock is normally the reference oscillator/64 or the self-clocked rate/64.
Development Support This section refers to registers and control bits only by their names. A Freescale-provided equate or header file is used to translate these names into the appropriate absolute addresses. 12.3.1 BDC Registers and Control Bits The BDC has two registers: • The BDC status and control register (BDCSCR) is an 8-bit register containing control and status bits for the background debug controller. • The BDC breakpoint match register (BDCBKPT) holds a 16-bit breakpoint match address.
Development Support 12.3.1.1 BDC Status and Control Register (BDCSCR) This register can be read or written by serial BDC commands (READ_STATUS and WRITE_CONTROL) but is not accessible to user programs because it is not located in the normal memory map of the MCU. 7 R 6 5 4 3 BKPTEN FTS CLKSW BDMACT ENBDM 2 1 0 WS WSF DVF W Normal Reset 0 0 0 0 0 0 0 0 Reset in Active BDM: 1 1 0 0 1 0 0 0 = Unimplemented or Reserved Figure 12-5.
Development Support Table 12-2. BDCSCR Register Field Descriptions (continued) Field Description 2 WS Wait or Stop Status — When the target CPU is in wait or stop mode, most BDC commands cannot function. However, the BACKGROUND command can be used to force the target CPU out of wait or stop and into active background mode where all BDC commands work.
Development Support R 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 BDFR1 W Reset 0 0 0 0 0 0 0 0 = Unimplemented or Reserved 1 BDFR is writable only through serial background mode debug commands, not from user programs. Figure 12-6. System Background Debug Force Reset Register (SBDFR) Table 12-3.
Development Support MC9S08QD4 Series MCU Data Sheet, Rev.
Appendix A Electrical Characteristics A.1 Introduction This chapter contains electrical and timing specifications. A.2 Absolute Maximum Ratings Absolute maximum ratings are stress ratings only, and functional operation at the maxima is not guaranteed. Stress beyond the limits specified in Table A-1 may affect device reliability or cause permanent damage to the device. For functional operating conditions, refer to the remaining tables in this section.
Appendix A Electrical Characteristics A.3 Thermal Characteristics This section provides information about operating temperature range, power dissipation, and package thermal resistance. Power dissipation on I/O pins is usually small compared to the power dissipation in on-chip logic and voltage regulator circuits and it is user-determined rather than being controlled by the MCU design.
Appendix A Electrical Characteristics A.4 ESD Protection and Latch-Up Immunity Although damage from electrostatic discharge (ESD) is much less common on these devices than on early CMOS circuits, normal handling precautions must be used to avoid exposure to static discharge. Qualification tests are performed to ensure that these devices can withstand exposure to reasonable levels of static without suffering any permanent damage.
Appendix A Electrical Characteristics Table A-5. DC Characteristics (Temperature Range = –40 to 125°C Ambient) Parameter Supply voltage (run, wait, and stop modes.) 1 POR re-arm voltage Minimum RAM retention supply voltage applied to VDD Symbol Min VDD 2.7 VPOR 0.9 VRAM VPOR Typical 1.4 2, 3 Max Unit 5.5 V 2.
Appendix A Electrical Characteristics Table A-5. DC Characteristics (continued)(Temperature Range = –40 to 125°C Ambient) Parameter Symbol Min Typical Max Unit High impedance (off-state) leakage current (per pin) VIn = VDD or VSS, all input/output |IOZ| — 0.025 1.0 μA Internal pullup resistors4 RPU 17.5 52.5 kΩ Internal pulldown resistor (IRQ) RPD 17.5 52.5 kΩ Output high voltage — Low Drive (PTxDSn = 0) 5 V, ILoad = –2 mA 3 V, ILoad = –0.6 mA 5 V, ILoad = –0.4 mA 3 V, ILoad = –0.
Appendix A Electrical Characteristics 7 Power supply must maintain regulation within operating VDD range during instantaneous and operating maximum current conditions. If positive injection current (VIn > VDD) is greater than IDD, the injection current may flow out of VDD and could result in external power supply going out of regulation. Ensure external VDD load will shunt current greater than maximum injection current. This will be the greatest risk when the MCU is not consuming power.
Appendix A Electrical Characteristics Typical Low-side Driver (HDS) Characteristics, VDD = 5.0 V, PORTA 40 35 125 105 85 25 0 –40 30 IOL/mA 25 20 15 10 5 0 0 0.4 0.8 1.6 1.2 2 2.4 2.8 VOL/V Figure A-3. Typical Low-Side Driver (Sink) Characteristics High Drive (PTxDSn = 1), VDD = 5.0 V, VOL vs. IOL Typical Low-side Driver (HDS) Characteristics, VDD = 3.0 V, PORTA 14 125 12 105 85 8 25 6 0 4 –40 IOL/mA 10 2 0 0 0.2 0.4 0.6 0.8 VOL/V 1 1.2 1.4 1.6 Figure A-4.
Appendix A Electrical Characteristics Typical High-side Driver (LDS) Characteristics, VDD = 5.0 V, PORTA IOH/mA 0 –1 125 –2 105 –3 85 –4 25 –5 0 –6 –40 –7 –8 2.4 2.8 3.2 3.6 4 VOH/V 4.4 4.8 5.2 Figure A-5. Typical High-Side Driver (Source) Characteristics Low Drive (PTxDSn = 0), VDD = 5.0 V, VOH vs. IOH Typical High-side Driver (LDS) Characteristics, VDD = 3.0 V, PORTA 0 125 –0.5 105 IOH/mA –1 85 25 –1.5 0 –2 –40 –2.5 –3 1.6 1.8 2 2.2 2.4 VOH/V 2.6 2.8 3 Figure A-6.
Appendix A Electrical Characteristics Typical High-side Driver (HDS) Characteristics, VDD = 5.0 V, PORTA 0 125 105 85 25 0 –40 –5 IOH/mA –10 –15 –20 –25 –30 2.4 2.8 3.2 4 3.6 VOH/V 4.4 4.8 5.2 Figure A-7. Typical High-Side Driver (Source) Characteristics High Drive (PTxDSn = 1), VDD = 5.0 V, VOH vs. IOH Typical High-side Driver (HDS) Characteristics, VDD = 3.0 V, PORTA 0 125 105 85 25 0 –40 –2 IOH/mA –4 –6 –8 –10 –12 1.6 1.8 2 2.2 2.4 VOH/V 2.6 2.8 3 Figure A-8.
Appendix A Electrical Characteristics A.6 Supply Current Characteristics This section includes information about power supply current in various operating modes Table A-6.
Appendix A Electrical Characteristics 3 All modules except ADC active, and does not include any dc loads on port pins Every unit tested to this parameter. All other values in the Max column are guaranteed by characterization. 5 All modules except ADC active, and does not include any dc loads on port pins 6 Every unit tested to this parameter. All other values in the Max column are guaranteed by characterization.
Appendix A Electrical Characteristics A.7 Internal Clock Source Characteristics Table A-7. Internal Clock Source Specifications Symbol Min Typ1 Max Unit Average internal reference frequency - untrimmed fint_ut 25 31.25 41.66 kHz Average internal reference frequency - trimmed fint_t — 31.25 — kHz DCO output frequency range - untrimmed fdco_ut 12.8 16 21.33 MHz DCO output frequency range - trimmed fdco_t — 16 — MHz — — ± 0.
Appendix A Electrical Characteristics Deviation of DCO Output from Trimmed Frequency (8 MHz, 5.5 V) 0.80% 0.70% 0.60% 0.50% Deviation 0.40% 0.30% 0.20% 0.10% 0.00% –0.10% –0.20% –0.30% –0.40% –40 –20 0 20 40 60 Temp. /C 80 100 120 140 Figure A-10. Typical Deviation of DCO Output vs. Temperature Deviation of DCO Output from Trimmed Frequency (8 MHz, 25 °C) 0.20% 0.15% Deviation 0.10% 0.05% 0.00% –0.05% –0.10% –0.15% –0.20% 2.5 3 3.5 4 4.5 5 5.5 6 VDD / V Figure A-11.
Appendix A Electrical Characteristics A.8 AC Characteristics This section describes AC timing characteristics for each peripheral system. A.8.1 Control Timing Table A-8. Control Timing Symbol Min Typical1 Max Unit Bus frequency (tcyc = 1/fBus) fBus 1 — 8 MHz Real-time interrupt internal oscillator period tRTI 700 — 1300 μs textrst 100 — — ns IRQ pulse width Asynchronous path2 Synchronous path3 tILIH, tIHIL 100 1.
Appendix A Electrical Characteristics tIHIL IRQ/KBIPx IRQ/KBIPx tILIH Figure A-13. IRQ/KBIPx Timing A.8.2 Timer/PWM (TPM) Module Timing Synchronizer circuits determine the shortest input pulses that can be recognized or the fastest clock that can be used as the optional external source to the timer counter. These synchronizers operate from the current bus rate clock. Table A-9.
Appendix A Electrical Characteristics A.9 ADC Characteristics Table A-10. ADC Characteristics Characteristic Supply Current ADLPC = 1 ADLSMP = 1 ADCO = 1 Conditions Symb VDDAD < 3.6 V (3.0 V Typ) VDDAD < 5.5 V (5.0 V Typ) Supply Current ADLPC = 1 ADLSMP = 0 ADCO = 1 VDDAD < 3.6 V (3.0 V Typ) Supply Current ADLPC = 0 ADLSMP = 1 ADCO = 1 VDDAD < 3.6 V (3.0 V Typ) Supply Current ADLPC = 0 ADLSMP = 0 ADCO = 1 VDDAD < 3.6V (3.0 V Typ) Supply Current Stop, Reset, Module Off VDDAD < 5.5 V (5.
Appendix A Electrical Characteristics Table A-10. ADC Characteristics (continued) Characteristic Zero-Scale Error Full-Scale Error Quantization Error Conditions 10 bit mode Symb EZS 8 bit mode 10 bit mode EFS 8 bit mode 10 bit mode EQ Min Typ1 Max 0 ±1.5 ±3.1 0 ±0.5 ±0.7 0 ±1.0 ±1.5 0 ±0.5 ±0.5 — — ±0.5 Unit Comment LSB VADIN = VSSA LSB VADIN = VDDA LSB 8 bit mode is not truncated 1 Typical values assume VDDAD = 5.0 V, Temp = 25°C, fADCK=1.0 MHz unless otherwise stated.
Appendix A Electrical Characteristics MC9S08QD4 Series MCU Data Sheet, Rev.
Appendix B Ordering Information and Mechanical Drawings B.1 Ordering Information This section contains ordering numbers for the devices. Table B-1. Device Numbering System Memory Device Number1 1 B.1.1 • Available Packages Qualification Flash RAM Type Type MC9S08QD4 MC9S08QD2 4 KB 2 KB 256 B 128 B 8 PDIP 8 NB SOIC Consumer and Industrial S9S08QD4 S9S08QD2 4 KB 2 KB 256 B 128 B 8 NB SOIC Automotive See Table 1-2 for a complete description of modules included on each device.
Appendix B Ordering Information and Mechanical Drawings B.2 Mechanical Drawings The following pages are mechanical specifications for the package options. See Table B-2 for the document number of each package type. Table B-2. Package Information Pin Count Type Designator Document No. 8 PDIP PC 98ASB42420B 8 NB SOIC SC 98ASB42564B MC9S08QD4 Series MCU Data Sheet, Rev.
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