Datasheet

MC9S08MP16 Series Data Sheet, Rev. 2
Electrical Characteristics
Freescale Semiconductor30
2.14.4 SPI
Table 19 and Figure 22 through Figure 25 describe the timing requirements for the SPI system.
Table 19. SPI Electrical Characteristics
Num
1
1
Refer to Figure 22 through Figure 25.
CRating
2
2
All timing is shown with respect to 20% V
DD
and 70% V
DD
, unless noted; 100 pF load on all SPI pins. All
timing assumes slew rate control disabled and high drive strength enabled for SPI output pins.
Symbol Min Max Unit
1D
Cycle time
Master
Slave
t
SCK
t
SCK
2
4
4096
—
t
cyc
t
cyc
2D
Enable lead time
Master
Slave
t
Lead
t
Lead
—
1/2
1/2
—
t
SCK
t
SCK
3D
Enable lag time
Master
Slave
t
Lag
t
Lag
—
1/2
1/2
—
t
SCK
t
SCK
4D
Clock (SPSCK) high time
Master and Slave
t
SCKH
1/2 t
SCK
– 25 — ns
5D
Clock (SPSCK) low time
Master and Slave
t
SCKL
1/2 t
SCK
– 25 — ns
6D
Data setup time (inputs)
Master
Slave
t
SI(M)
t
SI(S)
30
30
—
—
ns
ns
7D
Data hold time (inputs)
Master
Slave
t
HI(M)
t
HI(S)
30
30
—
—
ns
ns
8D
Access time, slave
3
3
Time to data active from high-impedance state.
t
A
040ns
9D
Disable time, slave
4
4
Hold time to high-impedance state.
t
dis
—40ns
10 D
Data setup time (outputs)
Master
Slave
t
SO
t
SO
—
—
25
25
ns
ns
11 D
Data hold time (outputs)
Master
Slave
t
HO
t
HO
–10
–10
—
—
ns
ns
12 D
Operating frequency
Master (SPIFE=0)
Slave (SPIFE=0)
Master (SPIFE=1)
Slave (SPIFE=1)
f
op
f
Bus
/4096
dc
f
Bus
/4096
dc
8
5
f
Bus
/4
5
6
5
6
5
Maximum baud rate must be limited to 8 MHz.
6
Maximum baud rate must be limited to 5 MHz due to input filter characteristics.
MHz
MHz
MHz