Datasheet

Electrical Characteristics
MC9S08MP16 Series Data Sheet, Rev. 2
Freescale Semiconductor 27
2.14 AC Characteristics
This section describes timing characteristics for each peripheral system.
2.14.1 Control Timing
4 D Differential input voltage V
DIFFMAX
0 V
5 T Linearity (@ voltage gain)
1
•1x
•2x
•4x
•8x
•16x
•32x
L
V
1 – 1/2 LSB
2 – 1/2 LSB
4 – 1 LSB
8 – 1 LSB
16 – 4 LSB
32 – 4 LSB
1
2
4
8
16
32
1 + 1/2 LSB
2 + 1/2 LSB
4 + 1 LSB
8 + 1 LSB
16 + 4 LSB
32 + 4 LSB
V/V
6 T Max gain error E
G
—1 2%
7a D PGA clock
• normal mode (LP=0)
• low power mode (LP=1)
f
PGA
—
—
8
2
4
8
2
4
MHz
7b D PGA sampling frequency
3
f
SAMPL
— — Samples
per second
8 D Input signal bandwidth BW 0 f
SAMPL
 8 f
SAMPL
 2Hz
9 D Charge pump clock frequency f
cpclk
100 f
PGA
 4—Hz
1
LSB in 12-bit resolution
2
8 MHz is required for PGA achieving 1 s sampling time.
3
ADC in 12-bit mode, long sampling time, f
ADC
=f
PGA
Table 16. Control Timing
Num C Rating Symbol Min Typ
1
Max Unit
1D
Bus frequency
(t
cyc
= 1/f
Bus
)
–40 to 105 Cf
Bus
DC — 25.67 MHz
–40 to 125 Cf
Bus
DC — 20 MHz
2 P Internal low power oscillator period t
LPO
700 — 1300 s
3 D External reset pulse width
2
t
extrst
100 — — ns
4 D Reset low drive t
rstdrv
34 x t
cyc
——ns
5 D BKGD/MS setup time after issuing background debug force
reset to enter user or BDM modes
t
MSSU
500 — — ns
6 D BKGD/MS hold time after issuing background debug force
reset to enter user or BDM modes
3
t
MSH
100 — — s
Table 15. Programmable Gain Amplifier Electrical Specifications (continued)
Num C Parameter Symbol Min Typical Max Unit
V
DDA
1.4–
2 Gain
------------------------------
–()
V
DDA
1.4–
2 Gain
------------------------------
1
12 18 NUM_CLK_GS+
f
PGA
------------------------------------------------------------------


43
f
ADC
-------------
5
f
BUS
-------------++
----------------------------------------------------------------------------------------------------