Datasheet
MC9S08MP16 Series Data Sheet, Rev. 2
Electrical Characteristics
Freescale Semiconductor22
4
P
DCO output frequency range —
trimmed
2
Low range (DRS=00)
f
dco_t
16 — 20
MHzC Mid range (DRS=01) 32 — 40
P High range (DRS=10) 48 — 60
5
P
DCO output frequency
2
Reference = 32768 Hz and
DMX32 = 1
Low range (DRS=00)
f
dco_DMX32
— 19.92 —
MHzP Mid range (DRS=01) — 39.85 —
P High range (DRS=10) — 59.77 —
6C
Resolution of trimmed DCO output frequency at fixed voltage and
temperature (using FTRIM)
f
dco_res_t
— 0.1 0.2
%f
dco
7C
Resolution of trimmed DCO output frequency at fixed voltage and
temperature (not using FTRIM)
f
dco_res_t
— 0.2 0.4
%f
dco
8P
Total deviation of trimmed DCO output frequency over voltage and
temperature
f
dco_t
— 0.8 2
%f
dco
9C
Total deviation of trimmed DCO output frequency over fixed voltage
and temperature range of 0
C to 70 C
f
dco_t
— 0.5 1
%f
dco
10 C
FLL acquisition time
3
t
Acquire
—— 1ms
11 C
Long term jitter of DCO output clock (averaged over 2-ms interval)
4
C
Jitter
— 0.02 0.2
%f
dco
1
Data in Typical column was characterized at 3.0 V, 25C or is typical recommended value.
2
The resulting bus clock frequency should not exceed the maximum specified bus clock frequency of the device.
3
This specification applies to any time the FLL reference source or reference divider is changed, trim value changed or changing
from FLL disabled (FBELP, FBILP) to FLL enabled (FEI, FEE, FBE, FBI). If a crystal/resonator is being used as the reference,
this specification assumes it is already running.
4
Jitter is the average deviation from the programmed frequency measured over the specified interval at maximum f
Bus
.
Measurements are made with the device powered by filtered supplies and clocked by a stable external clock signal. Noise injected
into the FLL circuitry via V
DD
and V
SS
and variation in crystal oscillator frequency increase the C
Jitter
percentage for a given
interval.
Table 10. ICS Frequency Specifications (continued)
Num C Characteristic Symbol Min Typ
1
Max Unit