Datasheet

MC9S08LL16 Series MCU Data Sheet, Rev. 7
Electrical Characteristics
Freescale Semiconductor32
Figure 20. Timer Input Capture Pulse
3.10.3 SPI Timing
Table 15 and Figure 21 through Figure 24 describe the timing requirements for the SPI system.
Table 15. SPI Timing
No. C Function Symbol Min Max Unit
—
D
Operating frequency
Master
Slave
f
op
f
Bus
/2048
0
f
Bus
/2
f
Bus
/4
Hz
D
SPSCK period
Master
Slave
t
SPSCK
2
4
2048
—
t
cyc
t
cyc
D
Enable lead time
Master
Slave
t
Lead
1/2
1
—
—
t
SPSCK
t
cyc
D
Enable lag time
Master
Slave
t
Lag
1/2
1
—
—
t
SPSCK
t
cyc
D
Clock (SPSCK) high or low time
Master
Slave
t
WSPSCK
t
cyc
– 30
t
cyc
– 30
1024 t
cyc
—
ns
ns
D
Data setup time (inputs)
Master
Slave
t
SU
15
15
—
—
ns
ns
D
Data hold time (inputs)
Master
Slave
t
HI
0
25
—
—
ns
ns
D Slave access time t
a
—1t
cyc
D Slave MISO disable time t
dis
—1t
cyc
D
Data valid (after SPSCK edge)
Master
Slave
t
v
—
—
25
25
ns
ns
t
ICPW
TPMCHn
t
ICPW
TPMCHn
1
2
3
4
5
6
7
8
9