Datasheet

Chapter 5 Resets, Interrupts, and System Configuration
MC9S08JM60 Series Data Sheet, Rev. 3
Freescale Semiconductor 75
must be written during the user’s reset initialization program to set the desired controls even if the desired
settings are the same as the reset settings.
76543210
R
COPT STOPE
00
W
Reset11010011
= Unimplemented or Reserved
Figure 5-5. System Options Register (SOPT1)
Table 5-5. SOPT1 Register Field Descriptions
Field Description
7:6
COPT[1:0]
COP Watchdog Timeout — These write-once bits select the timeout period of the COP. COPT along with
COPCLKS in SOPT2 defines the COP timeout period. See Ta bl e 5 -6 .
5
STOPE
Stop Mode Enable — This write-once bit defaults to 0 after reset, which disables stop mode. If stop mode is
disabled and a user program attempts to execute a STOP instruction, an illegal opcode reset is forced.
0 Stop mode disabled.
1 Stop mode enabled.
Table 5-6. COP Configuration Options
Control Bits
Clock Source
COP Window
1
Opens
(COPW = 1)
1
Windowed COP operation requires the user to clear the COP timer in the last 25% of the selected timeout period. This column
displays the minimum number of clock counts required before the COP timer can be reset when in windowed COP mode
(COPW = 1).
COP Overflow Count
COPCLKS COPT[1:0]
N/A 0:0 N/A N/A COP is disabled
0 0:1 1 kHz LPO
clock
N/A
2
5
cycles (32 ms
2
)
2
Values shown in milliseconds based on t
LPO
= 1 ms. See t
LPO
in the appendix Section A.12.1, “Control Timing,” for the
tolerance of this value.
0 1:0 1 kHz LPO
clock
N/A
2
8
cycles (256 ms
1
)
0 1:1 1 kHz LPO
clock
N/A
2
10
cycles (1.024 s
1
)
10:1
BUSCLK 6144 cycles
2
13
cycles
11:0
BUSCLK 49,152 cycles
2
16
cycles
11:1
BUSCLK 196,608 cycles
2
18
cycles