Datasheet

Chapter 4 Memory
MC9S08JM60 Series Data Sheet, Rev. 3
Freescale Semiconductor 55
Figure 4-3. Flash Burst Program Flowchart
4.5.5 Access Errors
An access error occurs whenever the command execution protocol is violated.
Any of the following specific actions will cause the access error flag (FACCERR) in FSTAT to be set.
FACCERR must be cleared by writing a 1 to FACCERR in FSTAT before any command can be processed.
• Writing to a flash address before the internal flash clock frequency has been set by writing to the
FCDIV register
• Writing to a flash address while FCBEF is not set (A new command cannot be started until the
command buffer is empty.)
• Writing a second time to a flash address before launching the previous command (There is only
one write to flash for every command.)
1
0
FCBEF ?
START
WRITE TO FLASH
TO BUFFER ADDRESS AND DATA
WRITE COMMAND (0x25) TO FCMD
NO
YES
FPVIO OR
WRITE 1 TO FCBEF
TO LAUNCH COMMAND
AND CLEAR FCBEF
(Note 2)
NO
YES
NEW BURST COMMAND ?
1
0
FCCF ?
ERROR EXIT
DONE
Note 2: Wait at least four bus cycles before
1
0
FACCERR ?
CLEAR ERROR
FACCERR ?
Note 1: Required only once after reset.
WRITE TO FCDIV
(Note 1)
checking FCBEF or FCCF.
FLASH BURST
PROGRAM FLOW