Datasheet

Appendix A Electrical Characteristics
MC9S08JM60 Series Data Sheet, Rev. 3
Freescale Semiconductor 367
Figure A-10. SPI Master Timing (CPHA = 0)
1
Refer to Figure A-10 through Figure A-13.
2
All timing is shown with respect to 20% V
DD
and 70% V
DD
, unless noted; 100 pF load on all SPI pins. All
timing assumes slew rate control disabled and high drive strength enabled for SPI output pins.
3
Time to data active from high-impedance state.
4
Hold time to high-impedance state.
SCK
(OUTPUT)
SCK
(OUTPUT)
MISO
(INPUT)
MOSI
(OUTPUT)
SS
1
(OUTPUT)
MSB IN
2
BIT 6 . . . 1
LSB IN
MSB OUT
2
LSB OUT
BIT 6 . . . 1
(CPOL = 0)
(CPOL = 1)
NOTES:
2. LSBF = 0. For LSBF = 1, bit order is LSB, bit 1, ..., bit 6, MSB.
1. SS
output mode (MODFEN = 1, SSOE = 1).
1
2 3
5
6
7
10 11
5
10
4
4