Datasheet

Appendix A Electrical Characteristics
MC9S08JM60 Series Data Sheet, Rev. 3
366 Freescale Semiconductor
Figure A-9. Timer Input Capture Pulse
A.12.3 SPI Characteristics
Table A-15 and Figure A-10 through Figure A-13 describe the timing requirements for the SPI system.
Table A-15. SPI Electrical Characteristic
Num
1
C Characteristic
2
Symbol Min Max Unit
1D
Operating frequency
Master
Slave
f
op
f
op
f
Bus
/2048
dc
f
Bus
/2
f
Bus
/4
Hz
2D
Cycle time
Master
Slave
t
SCK
t
SCK
2
4
2048
—
t
cyc
t
cyc
3D
Enable lead time
Master
Slave
t
Lead
t
Lead
—
1/2
1/2
—
t
SCK
t
SCK
4D
Enable lag time
Master
Slave
t
Lag
t
Lag
—
1/2
1/2
—
t
SCK
t
SCK
5D
Clock (SPSCK) high time Master and
Slave t
SCKH
1/2 t
SCK
– 25 — ns
6D
Clock (SPSCK) low time Master and
Slave t
SCKL
1/2 t
SCK
– 25 — ns
7D
Data setup time (inputs)
Master
Slave
t
SI(M)
t
SI(S)
30
30
—
—
ns
ns
8D
Data hold time (inputs)
Master
Slave
t
HI(M)
t
HI(S)
30
30
—
—
ns
ns
9 D Access time, slave
3
t
A
040ns
10 D Disable time, slave
4
t
dis
—40ns
11 D
Data setup time (outputs)
Master
Slave
t
SO
t
SO
25
25
—
—
ns
ns
12 D
Data hold time (outputs)
Master
Slave
t
HO
t
HO
–10
–10
—
—
ns
ns
t
ICPW
TPMxCHn
t
ICPW
TPMxCHn