Datasheet

Appendix A Electrical Characteristics
MC9S08JM60 Series Data Sheet, Rev. 3
364 Freescale Semiconductor
o
A.12 AC Characteristics
This section describes ac timing characteristics for each peripheral system.
A.12.1 Control Timing
4
Jitter is the average deviation from the programmed frequency measured over the specified interval at maximum f
BUS
.
Measurements are made with the device powered by filtered supplies and clocked by a stable external clock signal. Noise injected
into the FLL circuitry via V
DD
and V
SS
and variation in crystal oscillator frequency increase the C
Jitter
percentage for a given
interval.
5
Jitter measurements are based upon a 48 MHz MCGOUT clock frequency..
6
Below D
lock
minimum, the MCG is guaranteed to enter lock. Above D
lock
maximum, the MCG will not enter lock. But if the MCG
is already in lock, then the MCG may stay in lock.
7
Below D
unl
minimum, the MCG will not exit lock if already in lock. Above D
unl
maximum, the MCG is guaranteed to exit lock.
Table A-13. Control Timing
Num C Parameter Symbol Min Typ
1
1
Typical values are based on characterization data at V
DD
= 5.0 V, 25 °C unless otherwise stated.
Max Unit
1 Bus frequency (t
cyc
= 1/f
Bus
)f
Bus
dc — 24 MHz
2 Internal low-power oscillator period t
LPO
800 1500 μs
3 External reset pulse width
2
2
This is the shortest pulse that is guaranteed to be recognized as a reset pin request. Shorter pulses are not guaranteed to
override reset requests from internal sources.
t
extrst
100 — ns
4 Reset low drive t
rstdrv
66 x t
cyc
—ns
5 Active background debug mode latch setup time t
MSSU
500 — ns
6 Active background debug mode latch hold time t
MSH
100 — ns
7 IRQ pulse width
Asynchronous path
2
Synchronous path
3
3
This is the minimum pulse width that is guaranteed to pass through the pin synchronization circuitry. Shorter pulses may or
may not be recognized. In stop mode, the synchronizer is bypassed so shorter pulses can be recognized in that case.
t
ILIH,
t
IHIL
100
1.5 x t
cyc
——ns
8 KBIPx pulse width
Asynchronous path
2
Synchronous path
3
t
ILIH,
t
IHIL
100
1.5 x t
cyc
——ns
9 Port rise and fall time
low output drive (PTxDS = 0), (load = 50 pF)
4
Slew rate control disabled (PTxSE = 0)
Slew rate control enabled (PTxSE = 1)
high output drive (PTxDS = 1), (load = 50 pF)
Slew rate control disabled (PTxSE = 0)
Slew rate control enabled (PTxSE = 1)
4
Timing is shown with respect to 20% V
DD
and 80% V
DD
levels. Temperature range –40 °C to 85 °C.
t
Rise
, t
Fall
—
—
—
—
40
75
11
35
ns