Datasheet

Appendix A Electrical Characteristics
MC9S08JM60 Series Data Sheet, Rev. 3
Freescale Semiconductor 363
A.11 MCG Specifications
Table A-12. MCG Frequency Specifications (Temperature Range = –40 to 125°C Ambient)
Num C Rating Symbol Min Typical Max Unit
1P
Internal reference frequency - factory trimmed at V
DD
=
5 V and temperature = 25 °C
f
int_ft
— 31.25 — kHz
2P
Average internal reference frequency – untrimmed
1
1
TRIM register at default value (0x80) and FTRIM control bit at default value (0x0).
f
int_ut
25 32.7 41.66 kHz
3 P Average internal reference frequency Q – user trimmed
f
int_t
31.25 — 39.0625 kHz
4 D Internal reference startup time
t
irefst
—60100μs
5—
DCO output frequency range - untrimmed
1
value provided for reference: f
dco_ut
= 1024 X f
int_ut
f
dco_ut
25.6 33.48 42.66 MHz
6 P DCO output frequency range - trimmed
f
dco_t
32 — 40 MHz
7C
Resolution of trimmed DCO output frequency at fixed
voltage and temperature (using FTRIM)
Δf
dco_res_t
— ±0.1 ±0.2
%f
dco
8C
Resolution of trimmed DCO output frequency at fixed
voltage and temperature (not using FTRIM)
Δf
dco_res_t
— ±0.2 ±0.4
%f
dco
9P
Total deviation of trimmed DCO output frequency over
voltage and temperature
Δf
dco_t
—
+0.5
–1.0
±2
%f
dco
10 C
Total deviation of trimmed DCO output frequency over
fixed voltage and temperature range of 0 –70
°C
Δf
dco_t
— ±0.5 ±1
%f
dco
11 C
FLL acquisition time
2
2
This specification applies to any time the FLL reference source or reference divider is changed, trim value changed or changing
from FLL disabled (BLPE, BLPI) to FLL enabled (FEI, FEE, FBE, FBI). If a crystal/resonator is being used as the reference, this
specification assumes it is already running.
t
fll_acquire
—— 1ms
12 D
PLL acquisition time
3
3
This specification applies to any time the PLL VCO divider or reference divider is changed, or changing from PLL disabled (BLPE,
BLPI) to PLL enabled (PBE, PEE). If a crystal/resonator is being used as the reference, this specification assumes it is already
running.
t
pll_acquire
—— 1ms
13 C
Long term Jitter of DCO output clock (averaged over
2ms interval)
4
C
Jitter
— 0.02 0.2
%f
dco
14 D VCO operating frequency
f
vco
7.0 — 55.0 MHz
15 D PLL reference frequency range
f
pll_ref
1.0 — 2.0 MHz
16 T
Long term accuracy of PLL output clock (averaged over
2 ms)
f
pll_jitter_2ms
—
0.590
5
—
%f
pll
17 T Jitter of PLL output clock measured over 625 ns
f
pll_jitter_625ns
—
0.566
5
—
%f
pll
18 D
Lock entry frequency tolerance
6
D
lock
±1.49 — ±2.98 %
19 D
Lock exit frequency tolerance
7
D
unl
±4.47 — ±5.97 %
20 D Lock time – FLL
t
fll_lock
——
t
fll_acquire+
1075(1/
f
int_t)
s
21 D Lock time – PLL
t
pll_lock
——
t
pll_acquire+
1075(1/
f
pll_ref)
s
22 D Loss of external clock minimum frequency – RANGE = 0
f
loc_low
(3/5) x f
int
— — kHz
23 D Loss of external clock minimum frequency – RANGE = 1
f
loc_high
(16/5) x f
int
— — kHz